# US 2013/0155786 A1 · Data sensing circuit and memory device including the same

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- Number: US 2013/0155786 A1
- Document ID: US20130155786A1
- Status: Published application
- Kind: A1
- Application number: 13/605,818
- Filed: 2012-09-06
- Published: 2013-06-20
- Earliest claimed: 2011-12-14
- Assignees: SK hynix Inc.
- Inventors: Kwang-Seok KIM
- Web page: https://patentgrep.com/patent/US20130155786A1

## CPC

- G11C 7/02: with means for avoiding parasitic signals
- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- G11C 11/4094: Bit-line management or control circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A data sensing circuit includes: a current source configured to supply a reference current to an output line; a switching precharging unit configured to couple an input line with the output line during a precharge operation of the input line; and a current sinking unit configured to sink a current from the output line in response to a voltage level of the input line.

## Claims

### Claim 1

A data sensing circuit, comprising:
a current source configured to supply a reference current to an output line;
a switching unit configured to couple an input line with the output line during a precharge operation of the input line; and
a current sinking unit configured to sink a current from the output line in response to a voltage level of the input line.

### Claim 2 (depends on 1)

The data sensing circuit of claim 1, further comprising:
a comparison unit configured to compare a voltage level of the output line with a voltage level of the reference current.

### Claim 3 (depends on 2)

The data sensing circuit of claim 2, wherein the reference current is supplied from the current source to the output line through a mirroring unit.

### Claim 4 (depends on 3)

The data sensing circuit of claim 3, wherein the current source and the comparison unit are shared by a plurality of data sensing circuits.

### Claim 5 (depends on 1)

The data sensing circuit of claim 1, wherein the switching unit is a transistor that forms a current path between the input line and the output line in response to a precharge signal, and
the current sinking unit is a transistor that forms a current path between a ground and the output line in response to a voltage level of the input line.

### Claim 6 (depends on 1)

The data sensing circuit of claim 1, wherein a data is loaded onto the input line after the precharge operation.

### Claim 7

A data sensing circuit, comprising:
an input line;
an output line;
a first transistor configured to couple the input line with the output line in response to a precharge signal; and
a second transistor configured to have a gate coupled with the input line and form a current path between the output line and a sinking end.

### Claim 8 (depends on 7)

The data sensing circuit of claim 7, wherein the first transistor is one of an NMOS transistor and a PMOS transistor, and
the second transistor is one of an NMOS transistor and a PMOS transistor.

### Claim 9 (depends on 7)

The data sensing circuit of claim 7, further comprising:
a current source configured to supply a reference current to the output line; and
a comparison unit configured to compare a voltage level of the output line with a voltage level of the reference current.

### Claim 10 (depends on 9)

The data sensing circuit of claim 9, wherein the precharge signal is enabled before a data is loaded onto the input line.

### Claim 11

A bit line sense amplifier, comprising:
a current source configured to supply a reference current to an output line;
a switching unit configured to couple a bit line with the output line during a precharge operation of the bit line; and
a current sinking unit configured to sink a current from the output line in response to a voltage level of the bit line.

### Claim 12 (depends on 11)

The bit line sense amplifier of claim 11, further comprising:
a comparison unit configured to compare a voltage level of the output line with a voltage level of the reference current and drive a data bus.

### Claim 13 (depends on 12)

The bit line sense amplifier of claim 12, wherein the reference current is supplied from the current source to the output line through a mirroring unit.

### Claim 14 (depends on 12)

The bit line sense amplifier of claim 12, further comprising:
a refresh operation unit configured to perform a refresh operation onto the bit line in response to the voltage level of the output line.

### Claim 15 (depends on 12)

The bit line sense amplifier of claim 12, further comprising:
a write operation unit configured to transfer a data of the data bus to the bit line.

### Claim 16

A memory device, comprising:
a memory cell;
a bit line onto which a data of the memory cell is loaded;
a current source configured to supply a reference current to an output line;
a switching unit configured to couple the bit line with the output line during a precharge operation of the bit line;
a current sinking unit configured to sink a current from the output line in response to a voltage level of the bit line; and
a comparison unit configured to compare a voltage level of the output line with a voltage level of the reference current and drive a data bus.

### Claim 17 (depends on 16)

The memory device of claim 16, wherein a data is loaded from the memory cell to the bit line after a precharge operation of the bit line.

### Claim 18

A data sensing circuit, comprising:
a current source configured to supply a reference current to an output line;
a current sinking unit configured to sink a current from the output line in response to a voltage level of the input line;
a comparison unit configured to compare a voltage level of the output line with a voltage level of the reference current and drive a data bus; and
a switching unit configured to transfer a voltage of the data bus to the input line during a precharge operation of the input line.

### Claim 19 (depends on 18)

The data sensing circuit of claim 18, wherein the reference current is supplied from the current source to the output line through a mirroring unit.

### Claim 20 (depends on 18)

The data sensing circuit of claim 18, wherein the data is loaded onto the input line after the precharge operation.