# US 2013/0155781 A1 · Fast-bypass memory circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0155781 A1 - Document ID: US20130155781A1 - Status: Published application - Kind: A1 - Application number: 13/327,693 - Filed: 2011-12-15 - Published: 2013-06-20 - Earliest claimed: 2011-12-15 - Assignees: NVIDIA Corporation - Inventors: Venkata Kottapalli; Scott Pitkethly; Christian Klingner; Matthew Gerlach - Web page: https://patentgrep.com/patent/US20130155781A1 ## CPC - G11C 7/1072: {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories} - H03K 3/012: Modifications of generator to improve response time or to decrease power consumption - G11C: STATIC STORES (semiconductor memory devices H10B) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A memory circuit in which a level of a first data input appears promptly at an output in response to a clock pulse received. The circuit includes a flip-flop triggered by the clock pulse and configured to receive the first data input and drive a second data input. The circuit also includes a first control input driven by the clock pulse, a second control input driven by the flip-flop and selection logic configured to receive the first and second data inputs and the first and second control inputs. The selection logic is configured to drive the output of the memory circuit to the level of the first data input or of the second data input depending on the first and second control inputs. ## Claims ### Claim 1 A memory circuit in which a level of a first data input appears promptly at an output in response to a clock pulse received, the circuit comprising: a flip-flop triggered by the clock pulse and configured to receive the first data input and drive a second data input; a first control input driven by the clock pulse; a second control input driven by the flip-flop; and selection logic configured to receive the first and second data inputs and the first and second control inputs, the selection logic configured to drive the output of the memory circuit to the level of the first data input or the level of the second data input depending on the first and second control inputs. ### Claim 2 (depends on 1) The memory circuit of claim 1 where receipt of the clock pulse triggers the flip-flop to store the level of the first data input, and where the output of the memory circuit is driven to the level of the first data input before the level of the first data input is stored. ### Claim 3 (depends on 2) The memory circuit of claim 2 where the output of the memory circuit is driven to the level of the first data input on receipt of the clock pulse in the selection logic. ### Claim 4 (depends on 3) The memory circuit of claim 3 further comprising a buffer through which the clock pulse triggers the flip-flop, the buffer delaying the triggering of the flip-flop relative to receipt of the clock pulse in the selection logic. ### Claim 5 (depends on 2) The memory circuit of claim 2 where the flip-flop includes: upstream memory logic that receives the first data input and drives the second control input; and downstream memory logic that receives the second control input and drives the second data input. ### Claim 6 (depends on 5) The memory circuit of claim 5 where the upstream memory logic is a clocked, sense-amplifier-type latch. ### Claim 7 (depends on 5) The memory circuit of claim 5 where the downstream memory logic is an unclocked RS-type latch. ### Claim 8 (depends on 5) The memory circuit of claim 5 where the upstream memory logic drives an additional third control input also received in the selection logic, where the second and third control inputs are maintained high prior to receipt of the clock pulse, and become complementary upon receipt of the clock pulse, and where the output of the memory circuit is driven to the level of the first data input only when both the first and second control inputs are high. ### Claim 9 (depends on 8) The memory circuit of claim 8 where the output of the memory circuit is driven to the level of the first data input only when each of the first, second, and third control inputs are high. ### Claim 10 (depends on 8) The memory circuit of claim 8 where the selection logic is configured to drive the output of the memory circuit to the level of the second data input when the output is not driven to the level of the first data input. ### Claim 11 (depends on 8) The memory circuit of claim 8 where the selection logic includes an inverting complex gate configured to receive, in addition to the first data input, an output-promoter input and an output-demoter input, and to furnish the output of the memory circuit. ### Claim 12 (depends on 11) The memory circuit of claim 11 where the selection logic is configured such that the output-demoter input becomes high only when the second data input and at least one of the first, second, and third control inputs are low. ### Claim 13 (depends on 11) The memory circuit of claim 11 where the selection logic is configured such that the output-promoter input becomes high only when the second data input is low or each of the first, second, and third control inputs are high. ### Claim 14 (depends on 1) The memory circuit of claim 1 where the flip-flop is a D-type flip flop. ### Claim 15 (depends on 1) The memory circuit of claim 1 where the selection logic includes a multiplexer. ### Claim 16 (depends on 1) The memory circuit of claim 1 where the selection logic and the flip-flop are fabricated from complementary metal-oxide-semiconductor elements. ### Claim 17 A method to make a level of a first data input appear promptly at an output of a memory circuit in response to a clock pulse received, the method comprising: driving a first control input with the clock pulse; triggering a flip-flop to store the level of the first data input on receipt of the clock pulse, the flip-flop configured to drive a second data input and a second control input; and in selection logic configured to receive the first and second data inputs and the first and second control inputs, driving the output of the memory circuit to the level of the first data input or of the second data input depending on the first and second control inputs, where the output is driven to the level of the first data input on receipt of the clock pulse in the selection logic, and before the level of the first data input is stored. ### Claim 18 (depends on 17) The method of claim 17 where the output of the memory circuit is driven to the level of the second data input as soon as the level of the first data input is stored. ### Claim 19 A memory circuit in which a level of a first data input appears promptly at an output in response to a clock pulse received, the circuit comprising: a flip-flop triggered by receipt of the clock pulse to store the level of the first data input and configured to drive a second data input; a first control input driven by the clock pulse; a second control input driven by the flip flop; selection logic configured to drive the output of the memory circuit to the level of the first data input or of the second data input depending on the first and second control inputs, the output being driven to the level of the first data input on receipt of the clock pulse in the selection logic and before the level of the first data input is stored; and a buffer through which the clock pulse triggers the flip-flop, the buffer delaying the triggering of the flip-flop relative to receipt of the clock pulse in the selection logic. ### Claim 20 (depends on 19) The memory circuit of claim 19 where the delay is suitable in duration to enable the memory circuit to absorb skew and jitter from the clock pulse.