# US 2013/0155779 A1 · Semiconductor storage device, host controlling the same, and memory system including the semiconductor storage device and the host

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- Number: US 2013/0155779 A1
- Document ID: US20130155779A1
- Status: Published application
- Kind: A1
- Application number: 13/325,479
- Filed: 2011-12-14
- Published: 2013-06-20
- Earliest claimed: 2011-12-14
- Assignees: Kabushiki Kaisha Toshiba
- Inventors: Makoto HAMADA
- Web page: https://patentgrep.com/patent/US20130155779A1

## CPC

- G11C 13/0021: {Auxiliary circuits}
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0061: {Timing circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 2207/2245: Memory devices with an internal cache buffer
- G11C 2213/71: Three dimensional array
- G11C 2213/72: Array wherein the access device being a diode
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

According to one embodiment, a semiconductor storage device includes a memory cell array, a data latch group. The memory cell array comprises a plurality of memory cells. The data latch group holds a first address or a second address of the memory cell and data. The data latch group comprises a first data latch unit and a second data latch unit, the first data latch unit holds write data to be written to any of the memory cells or read data read from the memory cell array and the first address or the second address, while the second data latch unit holds second write data or read data.

## Claims

### Claim 1

A semiconductor storage device comprising:
a memory cell array comprising a plurality of memory cells capable of holding data; and
a data latch group capable of holding a first address of the memory cell serving as a read target or a second address of the memory cell serving as a write target, and the data held by the memory cells,
wherein the data latch group comprises a plurality of data latch units including at least a first data latch unit and a second data latch unit,
the first data latch unit holds first write data to be written to any of the memory cells and a first write address corresponding to the first write data, or first read data read from the memory cell array and a first read address corresponding to the first read data, while the second data latch unit holds second write data to be written to any of the memory cells and a second write address corresponding to the second write data, or second read data read from the memory cell array and a second read address corresponding to the second read data.

### Claim 2 (depends on 1)

The device according to claim 1, further comprising:
a data I/O section receiving and outputting one of write data as the first and second write data and read data as the first and second read data,
wherein a number of the data latch units is set according to a difference between a rate of data transfer between the data I/O section and the data latch group and a rate of data transfer between the data latch group and the memory cell array.

### Claim 3 (depends on 2)

The device according to claim 2, further comprising:
a controller,
wherein the controller receives a third address indicative of the first data latch unit and a fourth address indicative of the second data latch unit, from the data latch group, and
the first data latch unit and the second data latch unit are allowed to hold the write data or read data in accordance with the third and fourth addresses.

### Claim 4 (depends on 3)

The device according to claim 3, wherein the memory cell array includes:
a first signal line formed along a first direction;
a second signal line formed along a second direction orthogonal to the first direction; and
the memory cells each provided near a first area where the first signal line and the second signal line cross each other, the memory cells being electrically connected together by the first signal lie and the second signal line,
each of the memory cells having one of a first status and a second status which are capable of being electrically determined.

### Claim 5 (depends on 1)

The device according to claim 1, further comprising:
a data I/O section configured to receive and output read data as the first and second read data and write data as the first and second write data;
a first data line configured to connect the data I/O section and the data latch group together; and
a second data line configured to connect the data latch group and the memory cell array together,
wherein data transfer on the second data line is faster than data transfer on the first data line.

### Claim 6 (depends on 5)

The device according to claim 5, wherein the number of the data latch units is set according to a difference in data transfer rate between the first data line and the second data line on which the data is transmitted.

### Claim 7 (depends on 6)

The device according to claim 6, wherein, for the data write, the data I/O section outputs the write data, the first write address and/or second write address of the memory cell serving as the write target, and a third address indicative of the first data latch unit and/or a fourth address indicative of the second data latch unit,
for the data read, the data I/O section outputs the first read address and/or second read address of the memory cell serving as the read target, and the third address and/or the fourth address.

### Claim 8

A controller outputting data capable of being held by memory cells, a first address of each of the memory cells capable of holding the data, and a second address indicative of each of a plurality of data units provided in a data latch group capable of holding the data and the first address.

### Claim 9 (depends on 8)

The controller according to claim 8, wherein before an operation of writing the data and an operation of reading the data, a number of the data latch units provided in the data latch unit is set according to a first rate of data transfer between the memory cell and the data latch group and a second rate of data transfer between the data latch group and the data I/O section.

### Claim 10 (depends on 9)

The controller according to claim 9, wherein a write command or a read command is issued which corresponds to the number of data latch units provided in the data latch group.

### Claim 11 (depends on 8)

The controller according to claim 8, wherein a command for determining usage of the data latch group is issued to the data latch group, and the write command and/or the read command is issued according to the usage,
wherein the usage is a status indicating whether the data latch group is loading the write data from the data I/O section or writing the loaded write data to the memory cell, or the data latch group is loading read data from the memory cell or transferring the loaded read data to the data I/O section, or the data latch group holds neither of the write data and the read data.

### Claim 12

A memory system comprising:
a semiconductor chip; and
a controller configured to control the semiconductor chip,
wherein the semiconductor chip includes:
a memory cell array comprising a plurality of memory cells capable of holding data;
a data latch group capable of holding write data to be written to the memory cell and a first address of the memory cell serving as a read target, and read data read from the memory cell and a first read address of the memory cell serving as a read target,
wherein the data latch group comprises a plurality of data latch units including at least a first data latch unit and a second data latch unit.

### Claim 13 (depends on 12)

The system according to claim 12, wherein, for a write of the data, the controller issues a write command including the write data, the first write address, and a third address indicative of the first data latch unit to the semiconductor chip, and
for a read of the data, the controller issues a read command including the second read address and a fourth address indicative of the second data latch unit to the semiconductor chip.

### Claim 14 (depends on 11)

The system according to claim 11, wherein the semiconductor chip further includes a data I/O section receiving and outputting the data from and to the controller,
wherein before an operation of writing the data and an operation of reading the data, the controller sets a number of the data latch units provided in the data latch unit according to a first rate of data transfer between the memory cell and the data latch group and a second rate of data transfer between the data latch group and the data I/O section.

### Claim 15 (depends on 13)

The system according to claim 13, wherein the memory cell array includes:
a first signal line formed along a first direction;
a second signal line formed along a second direction orthogonal to the first direction; and
the first memory cells each provided near a first area where the first signal line and the second signal line cross each other, the memory cells being electrically connected together by the first signal lie and the second signal line,
wherein each of the memory cells has one of a first status and a second status which are capable of being electrically determined.

### Claim 16 (depends on 15)

The system according to claim 15, further comprising:
a data I/O section receiving and outputting the read data and the write data;
a first data line connecting the data I/O section and the data latch group together; and
a second data line connecting the data latch group and the memory cell array together,
wherein data transfer on the second data line is faster than data transfer on the first data line.

### Claim 17 (depends on 16)

The system according to claim 16, wherein the number of the data latch units is set by the controller according to a difference in data transfer rate between the first data line and the second data line on which the data is transmitted.

### Claim 18 (depends on 12)

The system according to claim 12, wherein the write command and the read command transferred from the controller allow the first data latch unit to hold the write data to be written to the memory cell and the first address, while allowing the second data latch unit to hold read data read from the memory cell array or the second address of the memory cell serving as a read target.

### Claim 19 (depends on 12)

The system according to claim 12, wherein the write command transferred from the controller allows each of the first data latch unit and the second data latch unit in the semiconductor chip to hold the data to be written to the memory cell and the first address.

### Claim 20 (depends on 12)

The system according to claim 12, wherein the read command transferred from the controller allows each of the first data latch unit and the second data latch unit in the semiconductor chip to hold the data read from the memory cell and the second address of the memory cell serving as a read target.