# US 2013/0155774 A1 · Semiconductor device and control method of the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0155774 A1 - Document ID: US20130155774A1 - Status: Published application - Kind: A1 - Application number: 13/610,368 - Filed: 2012-09-11 - Published: 2013-06-20 - Earliest claimed: 2005-06-28 - Assignees: Spansion LLC - Inventors: Akira OGAWA; Masaru YANO - Web page: https://patentgrep.com/patent/US20130155774A1 ## CPC - G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)} - G11C 16/28: using differential sensing or reference cells, e.g. dummy cells - H10B 41/00: Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES ## Abstract The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened. ## Claims ### Claim 1 A semiconductor device comprising: means for comparing a voltage level at a reference cell data line with a predefined voltage level; and a first charging means operable to charge the reference cell data line when a voltage level at a reference cell data line is lower than a predefined voltage level during pre-charging the reference cell data line; a second charging means operable to charge the reference cell data line when a voltage level at a reference cell data line is lower than a predefined voltage level during pre-charging the reference cell data line; and means for storing data comprising a core cell, wherein the core cell comprises a first bit and a second bit. ### Claim 2 (depends on 1) The semiconductor device of claim 1, further comprising: an averaging means coupled to multiple reference cells, wherein the second charging means outputs an output from an average circuit. ### Claim 3 (depends on 1) The semiconductor device of claim 1, further comprising: means for sensing after pre-charging of the reference cell data line is finished. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein the core cell is a Silicon Oxide Nitride Oxide Silicon (SONOS) type memory cell. ### Claim 5 (depends on 2) The semiconductor device of claim 2, wherein the averaging means has a first average circuit outputting to the first current-voltage conversion circuit, and a second average circuit outputting an output thereof to the means for sensing. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein the second charging means comprises a differential circuit to which the voltage level at the reference cell data line and the predefined voltage level are input. ### Claim 7 A method for fabricating a semiconductor device, comprising: fabricating a first current-voltage conversion circuit coupled to a core cell data line; forming a second current-voltage conversion circuit coupled a reference cell data line; and manufacturing a charging circuit coupled to the reference cell data line, wherein said charging circuit is operable to pre-charge the reference cell data line. ### Claim 8 (depends on 7) The method of claim 7, further comprising: forming a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit. ### Claim 9 (depends on 7) The method of claim 7, further comprising: forming a compare circuit operable to compare a voltage level at the reference cell data line with a predefined voltage level. ### Claim 10 (depends on 9) The method of claim 9, wherein the charging circuit includes a FET having a gate connected to an output from the compare circuit and a source and a drain respectively connected to a voltage source and the reference cell data line. ### Claim 11 (depends on 7) The method of claim 7, wherein the second current-voltage conversion circuit has a differential circuit to which the voltage level at the reference cell data line and the predefined voltage level are input. ### Claim 12 (depends on 7) The method of claim 7, wherein the predefined voltage level is lower than a target voltage level for pre-charging the reference cell data line. ### Claim 13 (depends on 7) The method of claim 7, wherein the second current-voltage conversion circuit has an average circuit operable to average outputs from multiple reference cells. ### Claim 14 (depends on 8) The method of claim 8, wherein: the second current-voltage conversion circuit outputs an output thereof to the first current-voltage conversion circuit and to the sense amplifier; and the first current-voltage conversion circuit differentially amplifies the output from the core cell and the output from second current-voltage conversion circuit to output to the sense amplifier.