# US 2013/0155772 A1 · Semiconductor memory device and method of operating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0155772 A1 - Document ID: US20130155772A1 - Status: Published application - Kind: A1 - Application number: 13/601,181 - Filed: 2012-08-31 - Published: 2013-06-20 - Earliest claimed: 2011-12-20 - Assignees: SK hynix Inc. - Inventors: Jong Soon LEEM - Web page: https://patentgrep.com/patent/US20130155772A1 ## CPC - G11C 16/10: Programming or data input circuits - G11C 16/12: Programming voltage switching circuits - G11C 16/24: Bit-line control circuits - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract In a semiconductor memory device and a method of operating the same, a memory block including memory cells is divided into memory groups. A level of bit line voltage applied to a bit line coupled to the memory cells included in each of the memory groups varies according to a distance between a row decoder and each memory groups during a program operation. Characteristics of the threshold voltage distribution of the memory cells in the semiconductor memory device may be improved without deteriorating performance of the program. ## Claims ### Claim 1 A method of semiconductor memory device comprising: a memory block having memory groups, each including cell strings coupled to word lines; a row decoder configured to apply a program voltage to a selected word line during a program operation; and a bit line voltage supply circuit configured to apply a bit line voltage into a bit line coupled to a program target cell determined according to input data among memory cells coupled to the selected word line, wherein a level of the bit line voltage varies according to a distance between the row decoder and the memory group including the program target cell. ### Claim 2 (depends on 1) The semiconductor memory device of claim 1, wherein the bit line voltage supply circuit applies a program inhibition voltage to a bit line coupled to a program inhibition cell among the memory cells. ### Claim 3 (depends on 1) The semiconductor memory device of claim 1, wherein the bit line voltage supply circuit applies a voltage for discharging the bit line to the bit line coupled to the program target cell included in the memory group having the highest distance from the row decoder. ### Claim 4 (depends on 1) The semiconductor memory device of claim 1, wherein the bit line voltage supply circuit applies the voltage having a higher magnitude to the bit line coupled to the program target cell according as a distance between the row decoder and the memory group including the program target cell is small. ### Claim 5 (depends on 1) The semiconductor memory device of claim 1, wherein each of the memory groups includes one cell string. ### Claim 6 A semiconductor memory device comprising: a memory block having memory groups, each including cell strings coupled to word lines; a row decoder configured to apply a program voltage to a selected word line among the word lines during a program operation; page buffer groups including page buffers for applying a reference voltage to a bit line coupled to a program target cell determined according to input data among memory cells coupled to the selected word line; and a reference voltage supply circuit configured to provide the reference voltage to the page buffer groups corresponding to the memory groups, wherein a level of the reference voltage varies according to a distance between the row decoder and the memory group including the program target cell. ### Claim 7 (depends on 6) The semiconductor memory device of claim 6, wherein the page buffer includes: a latch for storing the input data temporarily; and a reference voltage transfer circuit for applying the reference voltage to the bit line according to the input data. ### Claim 8 (depends on 7) The semiconductor memory device of claim 7, wherein the reference voltage transfer circuit applies the reference voltage to the bit line coupled to the program target cell, while providing a program inhibition voltage to a bit line coupled to a program inhibition cell according to the input data. ### Claim 9 (depends on 6) The semiconductor memory device of claim 6, wherein the reference voltage supply circuit applies a voltage, discharging the bit line coupled to the program target cell included in the memory group, to a page buffer group corresponding to a memory group having the highest distance from the row decoder among the memory groups. ### Claim 10 (depends on 6) The semiconductor memory device of claim 6, wherein the reference voltage supply circuit applies the reference voltage having a higher magnitude to a page buffer group corresponding to the memory group including the program target cell according as a distance between the row decoder and the memory group is small. ### Claim 11 (depends on 6) The semiconductor memory device of claim 6, wherein each of the memory groups includes one cell string. ### Claim 12 A method of operating a semiconductor memory device, the method comprising: applying a first voltage to a bit line coupled to a program target cell among first memory cells coupled to a selected word line in a first memory group; applying a second voltage, different from the first voltage, to a bit line coupled to another program target cell among second memory cells coupled to the selected word line in a second memory group; and performing a program operation of storing data in the first and the second memory cells by providing a program voltage to the selected word line and applying a pass voltage to other word lines. ### Claim 13 (depends on 12) The method of claim 12, further comprising: applying a program inhibition voltage to a bit line coupled to a program inhibition cell among the memory cells coupled to the selected word line. ### Claim 14 (depends on 12) The method of claim 12, wherein the first voltage higher than the second voltage is applied to the bit line coupled to the program target cell, if a distance between a row decoder and the first memory group is smaller than that between the row decoder and the second memory group. ### Claim 15 (depends on 12) The method of claim 12, wherein each of the first memory group and the second memory group includes one cell string.