# US 2013/0155770 A1 · Semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0155770 A1 - Document ID: US20130155770A1 - Status: Published application - Kind: A1 - Application number: 13/714,953 - Filed: 2012-12-14 - Published: 2013-06-20 - Earliest claimed: 2011-12-16 - Assignees: Samsung Electronics Co., Ltd. - Inventors: Makoto HIRANO - Web page: https://patentgrep.com/patent/US20130155770A1 ## CPC - G11C 16/24: Bit-line control circuits - G11C 7/227: {Timing of memory operations based on dummy memory elements or replica circuits} - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/32: Timing circuits - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A semiconductor memory device includes a memory cell array having a plurality of bit lines and a plurality of word lines intersecting each other and a plurality of nonvolatile memory cells; and a page buffer for each bit line including a latch configured to store one of data to be written to a first nonvolatile memory cell selected by each word line and data read from the first nonvolatile memory cell, wherein before reading out data, the page buffer configured to store in a replica capacitor a voltage value of a word line adjacent to the selected word line when a second nonvolatile memory cell is turned on, the replica capacitor including a first capacitor and a second capacitor connected in parallel, and the page buffer is configured to vary when the latch judges the data from the first nonvolatile memory cell according to the voltage value. ## Claims ### Claim 1 A semiconductor memory device comprising: a memory cell array including a plurality of bit lines and a plurality of word lines intersecting each other and a plurality of nonvolatile memory cells at intersections of the bit lines and the word lines; and a page buffer for each bit line including a latch configured to store one of data to be written to a nonvolatile memory cell selected by each word line and data read from the nonvolatile memory cell, wherein before reading out data from a first nonvolatile memory cell connected to a selected word line, the page buffer is configured to store in a replica capacitor a voltage value of a word line adjacent to the selected word line when a second nonvolatile memory cell is turned on, the second nonvolatile memory cell connected to the adjacent word line and written later than the first nonvolatile memory cell, the page buffer is configured to vary when the latch judges the data from the first nonvolatile memory cell connected to the selected word line according to the voltage value of the adjacent word line stored in the replica capacitor, and the replica capacitor includes a first capacitor and a second capacitor connected in parallel, the first capacitor having a capacitance value scaled from a capacitance between a floating gate of the first nonvolatile memory cell and a floating gate of the second nonvolatile memory cell, and the second capacitor having a capacitance value scaled from a capacitance between the floating gate of the first nonvolatile memory cell and ground. ### Claim 2 (depends on 1) The memory device of claim 1, further comprising: a switch between the first and second capacitors of the replica capacitor, the switch configured to be turned on or off by a change in an electric potential of a corresponding bit line, wherein the latch includes a data input teiniinal to which data is input and a clock input terminal to which a clock for latching the input data is input, and when the switch is turned on, the replica capacitor is configured to transfer electric charge accumulated in the first capacitor according to the voltage value of the adjacent word line to the second capacitor and vary input of the clock to the latch. ### Claim 3 (depends on 2) The memory device of claim 2, wherein the data from the first nonvolatile memory cell connected to the selected word line is input to the data input terminal, and the clock, which is delayed based on the stored voltage value of the adjacent word line, is input to the clock input terminal. ### Claim 4 (depends on 2) The memory device of claim 2, wherein data preset according to the data held in the first nonvolatile memory cell connected to the selected word line is input to the data input terminal, and the clock generated by accelerating a change in the data from the first nonvolatile memory cell according to the stored voltage value of the adjacent word line is input to the clock input terminal. ### Claim at position 5 -8. (canceled) ### Claim 9 A semiconductor memory device comprising: a page buffer for each bit line of a plurality of bit lines, each page buffer including, a latch configured to store one of data to be written to a first nonvolatile memory cell selected by a first word line of a plurality of word lines and data read from the first nonvolatile memory cell, the first nonvolatile memory cell one of a plurality of nonvolatile memory cells at intersections of the plurality of bit lines and the plurality of word lines; and a replica capacitor network including at least a first capacitor and a second capacitor connected in parallel, wherein the page buffer is configured to store in the replica capacitor network a voltage value of a second word line adjacent to the first word line when a second nonvolatile memory cell is turned on, the second nonvolatile memory cell connected to the second word line and written later than the first nonvolatile memory cell, and the page buffer is configured to vary when the latch judges the data from the first nonvolatile memory cell according to the voltage value stored in the replica capacitor. ### Claim 10 (depends on 9) The semiconductor memory device of claim 9, wherein a ratio of the first capacitor to the second capacitor is the same as a ratio of a capacitance between a floating gate of the first nonvolatile memory cell and a floating gate of the second nonvolatile memory cell and a capacitance between the floating gate of the first nonvolatile memory cell and ground. ### Claim 11 A page buffer for each of a plurality of bit lines included in a memory array in a semiconductor memory device, the page buffer comprising: a latch configured to store one of data to be written to a first nonvolatile memory cell in the memory array and data read from the first nonvolatile memory cell based on a clock signal, the first nonvolatile memory cell selected by a first word line; a comparator configured to compare a first word line voltage to a reference voltage, the output of the comparator being input as the clock signal to the latch; and a replica capacitor network configured to store a second word line voltage of a second word line when a second nonvolatile memory cell is turned on, the second word line adjacent to the first word line, the replica capacitor network configured to vary the first word line voltage compared by the comparator. ### Claim 12 (depends on 11) The page buffer of claim 11, wherein the replica capacitor network includes at least a first capacitor and a second capacitor connected in parallel, a ratio of the first capacitor to the second capacitor the same as a ratio of a capacitance between a floating gate of the first nonvolatile memory cell and a floating gate of the second nonvolatile memory cell and a capacitance between the floating gate of the first nonvolatile memory cell and ground. ### Claim 13 (depends on 12) The page buffer of claim 12, further comprising: a first switch between the first and second capacitors of the replica capacitor network, the switch configured to be turned on or off by a change in an electric potential of the bit line, wherein the latch includes a data input terminal to which data is input and a clock input terminal to which the clock signal for latching the input data is input, and when the switch is turned on, the replica capacitor is configured to transfer electric charge accumulated in the first capacitor according to the second word line voltage to the second capacitor. ### Claim 14 (depends on 13) The page buffer of claim 13, further comprising: a delay circuit configured to delay the data read from the first nonvolatile memory cell based on a delay control signal. ### Claim 15 (depends on 14) The page buffer of claim 14, further comprising: a switching circuit configured to control the first switch and a second switch, the second switch configured to connect the first capacitor to the second word line voltage. ### Claim 16 (depends on 15) The page buffer of claim 15, wherein the switching circuit is configured to charge the first capacitor with the second word line voltage in a first state and configured to transfer the electric charge accumulated in the first capacitor to the second capacitor in a second state. ### Claim 17 (depends on 11) The page buffer of claim 11, wherein the replica capacitor network includes at least a first capacitor and a second capacitor connected in parallel, the first capacitor having a capacitance value scaled from a capacitance between a floating gate of the first nonvolatile memory cell and a floating gate of the second nonvolatile memory cell, and the second capacitor having a capacitance value scaled from a capacitance between the floating gate of the first nonvolatile memory cell and ground. ### Claim 18 (depends on 11) The page buffer of claim 11, wherein the first nonvolatile memory cell and the second nonvolatile memory cell are multi-value cells configured to store 2-bit data.