# US 2013/0155769 A1 · Non-Volatile Memory And Method With Improved First Pass Programming

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- Number: US 2013/0155769 A1
- Document ID: US20130155769A1
- Status: Published application
- Kind: A1
- Application number: 13/329,103
- Filed: 2011-12-16
- Published: 2013-06-20
- Earliest claimed: 2011-12-16
- Assignees: SanDisk Technologies LLC
- Inventors: Yan Li; Cynthia Hsu; Ken Oowada
- Web page: https://patentgrep.com/patent/US20130155769A1

## CPC

- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 16/3468: {Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A nonvolatile memory with a multi-pass programming scheme enables a page of multi-level memory cells to be programmed with reduced floating-gate to floating-gate perturbations (Yuping effect). The memory cells operate within a common threshold voltage range or window, which is partitioned into multiple bands to denote a series of increasingly programmed states. The series is divided into two halves, a lower set and a higher set. The memory cells are programmed in a first, coarse programming pass such that the memory cells of the page with target states from the higher set are programmed to a staging area near midway in the threshold window. In particular, they are programmed closer to their targeted destinations than previous schemes, without incurring much performance penalty. Subsequent passes will then complete the programming more quickly. Yuping effect is reduced since the threshold voltage change in subsequent passes are reduced.

## Claims

### Claim 1

A method of programming a nonvolatile memory, comprising:
providing the nonvolatile memory with an array of memory cells, each memory cell having a common range of threshold voltages defining a threshold window;
configuring each memory cell to store N bits of data by partitioning the threshold window into 2N=k+1 bands of threshold voltages using k demarcation points D(i), where a lowest band denotes an erased state and is followed by k increasing bands that denotes k increasing programmed states P(i);
providing a programming voltage as a series of pulses;
programming in multiple programming passes a page of memory cells on a selected word line to respective target states;
said multiple programming passes including a first programming pass and one of more subsequent programming passes to program all memory cells of the page to respective target states; and wherein the first programming pass further comprises:
programming and verifying pulse by pulse a first set memory cells of the page having target states among an upper half of the k increasing programmed states, beginning with P([k+1]/2) and ending with P(k);
said verifying is relative to a predetermined threshold voltage, the predetermined verify threshold voltage is such that it enables verifying of programming of all the memory cells having target states being one of P([k+1]/2) to P(k) to be placed near the middle of the threshold window while not exceeding D([k+1]/2+1);
inhibiting programming of each memory cell of the first set that has been program-verified relative to the predetermined verify threshold voltage; and
after all memory cells of the first set have been program-verified relative to the predetermined verify threshold,
selectively disabling said inhibiting programming of each memory cell having a target state P([k+1]/2+x to programming with additional x pulses, without intervening program-verifying.

### Claim 2 (depends on 1)

The method as in claim 1, wherein:
the programming voltage in the first programming pass has pulses that programs at a faster rate than that of the subsequent programming pass.

### Claim 3 (depends on 1)

The method as in claim 1, wherein N=2.

### Claim 4 (depends on 1)

The method as in claim 1, wherein N=3.

### Claim 5 (depends on 1)

The method as in claim 1, wherein the nonvolatile memory is flash memory.

### Claim 6 (depends on 1)

The method as in any claim 1, wherein the array of memory cells has NAND architecture.

### Claim 7 (depends on 1)

The method as in claim 1, wherein the nonvolatile memory is embodiment in a memory card.

### Claim 8

A method of programming a nonvolatile memory, comprising:
providing the nonvolatile memory with an array of memory cells, each memory cell having a common range of threshold voltages defining a threshold window;
configuring each memory cell to store N bits of data by partitioning the threshold window into 2N=k+1 bands of threshold voltages using k demarcation points D(i), where a lowest band denotes an erased state and is followed by k increasing bands that denotes k increasing programmed states P(i);
providing a programming voltage as a series of pulses;
programming in multiple programming passes a page of memory cells on a selected word line to respective target states;
said multiple programming passes including a first programming pass and one of more subsequent programming passes to program all memory cells of the page to respective target states; and wherein the first programming pass further comprises:
programming and verifying pulse by pulse a first set memory cells of the page having target states among an upper half of the k increasing programmed states, beginning with P([k+1]/2) and ending with P(k);
said verifying is relative to a predetermined threshold voltage, the predetermined verify threshold voltage is such that it enables verifying of programming of all the memory cells having target states being one of P([k+1]/2) to P(k) to be placed near the middle of the threshold window while not exceeding D([k+1]/2+1);
inhibiting programming of each memory cell of the first set that has been program-verified relative to the predetermined verify threshold voltage; and
while ongoing programming pulses are still being applied to the page of memory cells until all memory cells of the first set have been program-verified relative to the predetermined verify threshold,
selectively disabling said inhibiting programming of each memory cell having a target state P([k+1]/2+x) to programming with up to x additional ongoing programming pulses, without intervening program-verifying.

### Claim 9 (depends on 8)

The method as in claim 8, wherein:
the programming voltage in the first programming pass has pulses that programs at a faster rate than that of the subsequent programming pass.

### Claim 10 (depends on 8)

The method as in claim 8, wherein N=2.

### Claim 11 (depends on 8)

The method as in claim 8, wherein N=3.

### Claim 12 (depends on 8)

The method as in claim 8, wherein the nonvolatile memory is flash memory.

### Claim 13 (depends on 8)

The method as in any claim 8, wherein the array of memory cells has NAND architecture.

### Claim 14 (depends on 8)

The method as in claim 8, wherein the nonvolatile memory is embodiment in a memory card.

### Claim 15

A nonvolatile memory, comprising:
an array of memory cells, each memory cell having a common range of threshold voltages defining a threshold window;
each memory cell configured to store N bits of data by having the threshold window partitioned into 2N=k+1 bands of threshold voltages using k demarcation points D(i), where a lowest band denotes an erased state and is followed by k increasing bands that denotes k increasing programmed states P(i);
a power supply for providing a programming voltage as a series of pulses;
a control circuit for controlling programming in multiple programming passes a page of memory cells on a selected word line to respective target states;
said multiple programming passes including a first programming pass and one of more subsequent programming passes to program all memory cells of the page to respective target states; and wherein the first programming pass further comprises:
programming and verifying pulse by pulse a first set memory cells of the page having target states among an upper half of the k increasing programmed states, beginning with P([k+1]/2) and ending with P(k);
said verifying is relative to a predetermined threshold voltage, the predetermined verify threshold voltage is such that it enables verifying of programming of all the memory cells having target states being one of P([k+1]/2) to P(k) to be placed near the middle of the threshold window while not exceeding D([k+1]/2+1);
inhibiting programming of each memory cell of the first set that has been program-verified relative to the predetermined verify threshold voltage; and
after all memory cells of the first set have been program-verified relative to the predetermined verify threshold,
selectively disabling said inhibiting programming of each memory cell having a target state P([k+1]/2+x to programming with additional x pulses, without intervening program-verifying.

### Claim 16

A nonvolatile memory, comprising:
an array of memory cells, each memory cell having a common range of threshold voltages defining a threshold window;
each memory cell configured to store N bits of data by having the threshold window partitioned into 2N=k+1 bands of threshold voltages using k demarcation points D(i), where a lowest band denotes an erased state and is followed by k increasing bands that denotes k increasing programmed states P(i);
a power supply for providing a programming voltage as a series of pulses;
a control circuit for controlling programming in multiple programming passes a page of memory cells on a selected word line to respective target states;
said multiple programming passes including a first programming pass and one of more subsequent programming passes to program all memory cells of the page to respective target states; and wherein the first programming pass further comprises:
programming and verifying pulse by pulse a first set memory cells of the page having target states among an upper half of the k increasing programmed states, beginning with P([k+1]/2) and ending with P(k);
said verifying is relative to a predetermined threshold voltage, the predetermined verify threshold voltage is such that it enables verifying of programming of all the memory cells having target states being one of P([k+1]/2) to P(k) to be placed near the middle of the threshold window while not exceeding D([k+1]/2+1);
inhibiting programming of each memory cell of the first set that has been program-verified relative to the predetermined verify threshold voltage; and
while ongoing programming pulses are still being applied to the page of memory cells until all memory cells of the first set have been program-verified relative to the predetermined verify threshold,
selectively disabling said inhibiting programming of each memory cell having a target state P([k+1]/2+x) to programming with up to x additional ongoing programming pulses, without intervening program-verifying.