# US 2013/0155768 A1 · Method for Operating a High Density Multi-Level Cell Non-Volatile Flash Memory Device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2013/0155768 A1
- Document ID: US20130155768A1
- Status: Published application
- Kind: A1
- Application number: 13/327,586
- Filed: 2011-12-15
- Published: 2013-06-20
- Earliest claimed: 2011-12-15
- Assignees: Nanjing University
- Inventors: YUE XU; FENG YAN; LING PU; XIAOLI JI
- Web page: https://patentgrep.com/patent/US20130155768A1

## CPC

- G11C 11/5671: {using charge trapping in an insulator}
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 16/10: Programming or data input circuits
- G11C 16/3445: {Circuits or methods to verify correct erasure of nonvolatile memory cells}
- G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells}
- G11C 16/349: {Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A localized trapping multi-level memory cell operating method includes the following steps. First, a localized trapping memory cell with the initial threshold voltage of ˜2.5V is provided. Next, an erasing operation is performed to obtain a negative threshold level which has the uniform distribution along the channel region. Taking into account the over-erasure issue in the erasing course, a programming operation is performed to precisely adjust the threshold voltage to a predetermined level of −2V˜−1V. Then, with the negative voltage as a new initial state, corresponding programming operation is performed and electrons are locally injected the storage layer. By controlling the quantity of injected electrons, the MLC storage is achieved.

## Claims

### Claim 1

A Method for operating a high density multi-level cell non-volatile flash memory possesses the following operating steps:
(a) a localized trapping memory cell with initial threshold voltage of about 2 V˜3 V is erased to a new initial level of about −2 V˜−1 V, after erasing, stored bits at each side of a cell have a same threshold level, and a uniform charge distribution in a nitride layer along the channel is obtained;
(b) with the state of the negative threshold voltage of about −2 V−˜1 V as a new initial state, a MLC programming operation for the localized trapping memory is performed, a channel hot electron CHE injection is used with a positive substrate bias to suppress a secondary electron injection, or a pulse agitated substrate hot electron injection (PASHEI) programming method to implement the charge localized storage;
(c) By changing a gate or a drain voltage or a programming time, more than eight programming states, i.e. more than eight threshold voltage levels can be achieved.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the step (a) is performed by a double-side band-to-band tunneling hot hole (BBHH) erasing method, i.e. two equal positive voltages are applied on a source and the drain simultaneously, and a negative voltage is applied to a gate, while a substrate is grounded, thereby electrons trapped in a storage layer can be uniformly erased.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the step (a), in order to prevent over-erasing, i.e. a erased threshold voltage being less than a predetermined negative level, an impact ionization generated substrate hot electron (IIHE) programming method is applied, during the IIHE programming, two equal positive voltages are applied on a source and a drain simultaneously, and a positive voltage is applied on a gate, while a substrate is grounded, substrate hot electrons are generated from impact of accelerated hot hole and are uniformly injected into a storage layer, as a result, the threshold voltage increases and uniformly distributes along channel region.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the step (b) when the channel hot electron (CHE) injection with the positive substrate bias is applied, ˜2V is applied to a substrate, 3V˜5V and 5V˜8V are applied to a drain and a gate, respectively, with a source grounded, when the PASHEI programming method is applied, it consists of two stages, in the first stage, a −2 V pulse is applied between the drain and the substrate, ˜0.2V is applied to the gate, and the source is grounded, in the second stage, a 2.5V˜4V pulse is applied between the drain and the substrate, 4V˜5V is applied to the gate, and the source is grounded.

### Claim 5 (depends on 2)

The method according to claim 2, wherein the double side BBHH erasing method, i.e. a pulse of −4V˜−8V is applied to the gate, a bias of 4V˜6V is applied to the source and the drain and the substrate is grounded, generated holes in the source and the drain region are accelerated by a reverse electric field, they obtain enough energy to inject into the storage layer through a tunneling layer and recombine with the trapping electrons, when the great number of holes are trapped in the storage layer, the threshold voltage of memory cell reaches the negative level;
the erasing operation may also be performed by a negative Fowler-Nordheim (FN) mechanism, in this case, a bias of −8V−˜12 V is applied to the gate, and the source, the drain and the substrate are grounded, when a electric field in the tunneling layer reaches more than 10 MV/cm, holes are injected into the storage layer by the FN tunneling mechanism, when a great number of holes are trapped in the storage layer, the threshold voltage of memory cell reaches a negative level.

### Claim 6 (depends on 3)

The method according to claim 3, wherein a double side IIHE programming method, i.e. a pulse of 4V˜8V is applied to the gate, and a bias with 4V˜6V is applied to the source and the drain and the substrate is grounded, substrate hot electrons are generated from impact ionization of accelerated hot holes coming from the source and drain, generated electrons in the source and drain region are accelerated towards the gate by forward vertical electric field, after they obtain enough energy, they inject into the storage layer through the tunneling layer and recombine with the trapped electrons, as a result, the threshold voltage of memory cell increases, the double side IIHE programming ensures uniform charge distribution and threshold voltage distribution along a channel is obtained;
a programming operation may also be performed by FN programming mechanism, in this case, a bias with 8V˜12 V is applied to the gate, and the source, the drain and the substrate are grounded, when the electric field in the tunneling layer reaches more than 10 MV/cm, the electrons are injected into the storage layer by FN tunneling, as a result, the threshold voltage of memory cell increases.

### Claim 7 (depends on 4)

The method according to claim 4, wherein a CHE injection programming with positive substrate bias to prevent a second hot electron injection, i.e. ˜2V is applied to the substrate, 3V˜5V is applied to the drain, 5V˜8V is applied to the gate, and the source is grounded, as a positive bias is applied to the substrate, the second hot electron injection is effectively suppressed, as a result, hot electrons are injected the storage layer only near the drain junction, which improves the performances of the localized charge storage, by changing the drain programming voltage or programming time, more than eight programmed states can be obtained, if an eight-level 3-bit storage at each side of cell is achieved, the distribution width of each threshold voltage can reach 0.7V, thereby allowing enough spacing between different threshold voltage distributions;
the programming operation may also be performed by the PASHEI programming method, in this case, the programming course is divided into two stages, during a first stage, a −2 V pulse is applied to the drain, the gate is tied to 0.2V, and the substrate and the source are grounded, because a PN junction between the drain and the substrate is forward biased, a great number of electrons are generated, next, the programming enters the second stage, a drain voltage quickly changes to 2.5V˜4V in a short time and a gate voltage also increases to 4V˜5V, so, a junction between the substrate and the drain quickly changes from a forward bias to reverse bias, then, the generated electrons in the first stage are injected into a depletion region of drain junction by the reverse electric field, injected electrons are accelerated in the drain depletion region and a plenty of electron-hole pairs are generated by impact ionization, sdsome electrons gain enough energy over Si/SiO2 barrier and are injected into the storage layer near drain edge by a perpendicular electric field, by slightly changing the drain voltage in the second stage to control quantity of the injected electrons, a MLC storage can be obtained;
for different programmed states of MLC using the CHE with the positive substrate bias or the PASHEI programming mechanisms, a single side BBHH erasing mechanism is used to erase the programmed states of MLC devices to the erased state with a negative threshold voltage.

### Claim 8 (depends on 2)

The method according to claim 2, wherein there is a validation step, if a threshold voltage of a erased cell is higher than a erased predetermined level, the erase operation continues, otherwise, over-erasing occurs.

### Claim 9 (depends on 3)

The method according to claim 3, wherein there is a validation step, if a threshold voltage of a erased cell is higher than a erased predetermined level, the erase operation continues, otherwise, over-erasing occurs.