# US 2013/0155767 A1 · Apparatuses and methods for sensing a phase-change test cell and determining changes to the test cell resistance due to thermal exposure

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- Number: US 2013/0155767 A1
- Document ID: US20130155767A1
- Status: Published application
- Kind: A1
- Application number: 13/735,791
- Filed: 2013-01-07
- Published: 2013-06-20
- Earliest claimed: 2009-12-30
- Assignees: Micron Technology, Inc.
- Inventors: Jason Brand; Jason Snodgress
- Web page: https://patentgrep.com/patent/US20130155767A1

## CPC

- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 7/04: with means for avoiding disturbances due to temperature effects
- G11C 13/0033: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 29/50: Marginal testing, e.g. race, voltage or current testing
- G11C 13/00: Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C 2029/5002: {Characteristic}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A phase change memory array may include at least one cell used to determine whether the array has been altered by thermal exposure over time. The cell may be the same or different from the other cells. In some embodiments, the cell is only read in response to an event. If, in response to that reading, it is determined that the cell has changed state or resistance, it may deduce whether the change is a result of thermal exposure. Corrective measures may then be taken.

## Claims

### Claim 1

A method, comprising:
sensing a characteristic of a phase change test cell that is configured to be more sensitive to thermal degradation than phase change memory cells of a phase change memory array;
determining whether the sensed characteristic of the phase change test cell is within a tolerance range of an initial value; and
refreshing the phase change memory array responsive to a determination that the sensed characteristic of the phase change test cell is outside the tolerance range of the initial value.

### Claim 2 (depends on 1)

The method of claim 1, wherein determining whether the sensed characteristic of the phase change test cell is within the tolerance range of the initial value comprises comparing the sensed characteristic to the threshold.

### Claim 3 (depends on 1)

The method of claim 1, wherein sensing the characteristic of the phase change test cell comprises sensing a resistance of the phase change test cell.

### Claim 4 (depends on 3)

The method of claim 3, further comprising storing an initial resistance value of the phase change memory cell as the threshold value.

### Claim 5 (depends on 4)

The method of claim 4, further comprising measuring the initial resistance value of the phase change memory cell.

### Claim 6 (depends on 1)

The method of claim 1, further comprising refreshing the phase change memory array responsive to the determination that the sensed characteristic of the phase change test cell is less than the initial value.

### Claim 7 (depends on 1)

The method of claim 1, further comprising refreshing the phase change memory array responsive to the determination that the sensed characteristic of the phase change test cell is not equal to the initial value.

### Claim 8

A method, comprising:
writing data to a phase change test cell that is configured to be more sensitive to thermal degradation than phase change memory cells of a phase change memory array, wherein the data is associated with an initial state of the phase change test cell;
determining a state of the phase change test cell; and
refreshing the phase change memory array responsive to the state of the phase change test cell changing from the initial state.

### Claim 9 (depends on 8)

The method of claim 8, further comprising comparing the state of the phase change test cell with the initial state.

### Claim 10 (depends on 8)

The method of claim 8, further comprising resetting the phase change test cell after refreshing the phase change memory array.

### Claim 11 (depends on 8)

The method of claim 8, wherein determining the state of the phase change test cell is responsive to detection of an event.

### Claim 12 (depends on 11)

The method of claim 11, wherein the event comprises at least one of a power cycle, a number of read cycles, a number of write cycles, a time out, or combinations thereof.

### Claim 13 (depends on 8)

The method of claim 8, further comprising verifying the state of the phase change test cell responsive to the state of the phase change test cell changing from the initial state.

### Claim 14 (depends on 8)

The method of claim 8, wherein determining a state of the phase change test cell comprises determining a crystalline or amorphous state of the phase change test cell.

### Claim 15

An apparatus comprising:
a phase change memory cell formed using a first fabrication method;
a phase change test cell formed using a second fabrication method, wherein the phase change test cell is more sensitive to thermal degradation than the phase change memory cell, the phase change test cell configured in an initial state; and
a controller coupled to the phase change memory cell and to the phase change test cell, the controller configured to determine whether the phase change test cell has changed from the initial state.

### Claim 16 (depends on 15)

The apparatus of claim 15 wherein the controller is further configured to refresh the phase change memory cell responsive to a determination that the phase change test cell has changed from the initial state.

### Claim 17 (depends on 15)

The apparatus of claim 15 wherein the controller is further configured to reset the phase change test cell after the phase change test cell has changed from the initial state.

### Claim 18 (depends on 15)

The apparatus of claim 15 wherein the controller is further configured to reprogram the phase change test cell to the initial state responsive to a determination that a resistance of the phase change test cell has changed more than a first threshold amount from an initial amount.

### Claim 19 (depends on 18)

The apparatus of claim 18 wherein the controller is further configured to determine whether the phase change test cell is unreliable based on a difference between the resistance of the phase change test cell and the initial amount exceeds a second threshold amount.

### Claim 20 (depends on 15)

The apparatus of claim 15, wherein the phase change test cell is included in a phase change test array.

### Claim 21 (depends on 15)

The apparatus of claim 15, wherein the phase change test cell and the phase change memory cells are included in a phase change memory array.

### Claim 22

An apparatus comprising:
a phase change memory array; and
a controller coupled to the phase change memory array, the controller configured to measure a respective resistance of selected phase change memory cells of the phase change memory array, the controller further configured to determine whether the respective resistance of a phase change memory cell of the selected phase change memory cells has changed from a respective initial resistance by more than a threshold amount.

### Claim 23 (depends on 22)

The apparatus of claim 22, wherein the controller is further configured to refresh the phase change memory array responsive to a determination that a count of the selected phase change memory cells having the associated resistance change from the respective initial resistance by more than the threshold amount exceeds a refresh required count.

### Claim 24 (depends on 23)

The apparatus of claim 23, wherein the controller is further configured generate the count of the selected phase change memory cells having the associated resistance change from the respective initial resistance by more than the threshold amount.

### Claim 25 (depends on 22)

The apparatus of claim 22, wherein the selected phase change memory cells includes each phase change memory cell of the phase change memory array.

### Claim 26

A method, comprising:
measuring a respective resistance of selected phase change memory cells of a phase change memory array;
determining whether the respective resistance of a phase change memory cell of the selected phase change memory cells is within a tolerance range of a respective initial resistance; and
refreshing the phase change memory array responsive to a determination that a count of the selected phase change memory cells having the respective measured resistance outside the tolerance range of the respective initial resistance exceeds a refresh required count.

### Claim 27 (depends on 26)

The method of claim 26, further comprising generating the count of the selected phase change memory cells having the respective measured resistance outside the tolerance range of the respective initial resistance.

### Claim 28 (depends on 26)

The method of claim 26, further comprising:
determining a respective state of the selected phase change memory cells; and
refreshing the phase change memory array responsive to a determination that a second count of the selected phase change memory cells having the respective state that is different than a respective initial state exceeds a second refresh required count.

### Claim 29 (depends on 28)

The method of claim 28, wherein the first refresh required count is equal to the second refresh required count.

### Claim 30 (depends on 26)

The method of claim 26, wherein measuring the respective resistance of the selected phase change memory cells of the phase change memory array comprises measuring the respective resistance of the each phase change memory cell of the phase change memory array.