# US 2013/0155759 A1 · Test Structures, Methods of Manufacturing Thereof, Test Methods, and MRAM Arrays

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- Number: US 2013/0155759 A1
- Document ID: US20130155759A1
- Status: Published application
- Kind: A1
- Application number: 13/328,953
- Filed: 2011-12-16
- Published: 2013-06-20
- Earliest claimed: 2011-12-16
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Ya-Chen Kao; Tien-Wei Chiang; Chun-Jung Lin
- Web page: https://patentgrep.com/patent/US20130155759A1

## CPC

- G11C 11/14: using thin-film elements
- G11C 11/16: using elements in which the storage effect is based on magnetic spin effect
- G11C 29/00: Checking stores for correct operation {; Subsequent repair}; Testing stores during standby or offline operation
- G11C 29/50: Marginal testing, e.g. race, voltage or current testing
- H10P 74/27: {Structural arrangements therefor}
- H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers}
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- G11C 2029/5002: {Characteristic}
- H10N 50/01: Manufacture or treatment
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

Test structures, methods of manufacturing thereof, test methods, and magnetic random access memory (MRAM) arrays are disclosed. In one embodiment, a test structure is disclosed. The test structure includes an MRAM cell having a magnetic tunnel junction (MTJ) and a transistor coupled to the MTJ. The test structure includes a test node coupled between the MTJ and the transistor, and a contact pad coupled to the test node.

## Claims

### Claim 1

A test structure comprising:
a magnetic random access memory (MRAM) cell including a magnetic tunnel junction (MTJ) and a transistor coupled to the MTJ;
a test node coupled between the MTJ and the transistor; and
a contact pad coupled to the test node.

### Claim 2 (depends on 1)

The test structure according to claim 1, wherein the transistor comprises a bipolar junction transistor (BJT) or a complementary metal oxide semiconductor (CMOS) device.

### Claim 3 (depends on 1)

The test structure according to claim 1, wherein the MRAM cell comprises a spin-transfer torque (STT) switched MRAM cell.

### Claim 4 (depends on 1)

The test structure according to claim 1, wherein the test node comprises a first test node, further comprising a second test node coupled to the MTJ, a third test node coupled to a gate of the transistor, and a fourth test node coupled to a source or drain of the transistor.

### Claim 5 (depends on 4)

The test structure according to claim 4, wherein the transistor is disposed over a substrate, and wherein the test structure further comprises a fifth test node coupled to the substrate.

### Claim 6 (depends on 5)

An MRAM array including a test structure according to claim 5.

### Claim 7 (depends on 6)

The MRAM array according to claim 6, wherein the second test node is coupled to a bit-line of the MRAM array, wherein the third test node is coupled to a word-line of the MRAM array, and wherein the fourth test node is coupled to a select-line of the MRAM array.

### Claim 8 (depends on 7)

The MRAM array according to claim 7, wherein the word-line is disposed over the substrate, wherein the select-line is disposed over the word-line in a first metallization layer, wherein the first test node is disposed in the first metallization layer, and wherein the bit-line is disposed in a second metallization layer disposed over the first metallization layer.

### Claim 9 (depends on 6)

The MRAM array according to claim 6, wherein the MRAM array comprises a plurality of rows of MRAM cells and a plurality of columns of MRAM cells, and wherein the MRAM cell of the test structure comprises an MRAM cell in one of the plurality of rows of MRAM cells and one of the plurality of columns of MRAM cells of the MRAM array.

### Claim 10 (depends on 6)

The MRAM array according to claim 6, wherein the MRAM array includes a plurality of rows of MRAM cells and a plurality of columns of MRAM cells, wherein the MRAM array includes a plurality of test structures, and wherein one of the plurality of test structures is included each of the plurality of columns of MRAM cells.

### Claim 11

A method of manufacturing a test structure, the method comprising:
forming a plurality of magnetic random access memory (MRAM) cells over a workpiece, each MRAM cell including a magnetic tunnel junction (MTJ) and a transistor coupled to the MTJ;
coupling a test node to one of the plurality of MRAM cells between the MTJ and the transistor; and
coupling a contact pad to the test node.

### Claim 12 (depends on 11)

The method according to claim 11, wherein coupling the contact pad to the test node comprises forming the contact pad on a surface of a semiconductor device including the plurality of MRAM cells, and coupling the contact pad to a connection between the MTJ and the transistor.

### Claim 13 (depends on 12)

The method according to claim 12, wherein coupling the contact pad to the connection between the MTJ and the transistor comprises forming a plurality of conductive segments and vias in a plurality of metallization layers of the semiconductor device.

### Claim 14 (depends on 13)

The method according to claim 13, wherein manufacturing the test structure comprises forming a test key.

### Claim 15

A testing method, including:
providing a test structure, the test structure comprising a magnetic random access memory (MRAM) cell including a magnetic tunnel junction (MTJ) and a transistor coupled to the MTJ, the test structure comprising a test node coupled between the MTJ and the transistor, wherein the test structure is coupled to a bit-line, a word-line, and a select-line and is disposed over a substrate; and
performing a test on a portion of the test structure using a combination of at least two of the test node, the bit-line, the word-line, the select-line, and the substrate.

### Claim 16 (depends on 15)

The method according to claim 15, wherein performing the test comprises determining a characteristic of or measuring a performance of the MTJ, the transistor, or both the MTJ and the transistor.

### Claim 17 (depends on 15)

The method according to claim 15, wherein the bit-line is coupled to the MTJ, the word-line is coupled to a gate of the transistor, the select-line is coupled to a source or drain of the transistor, and the test node is coupled to a drain or source of the transistor.

### Claim 18 (depends on 17)

The method according to claim 17, wherein performing the test comprises performing the test on the MTJ using the test node and the bit-line, and wherein the test comprises a resistance-magnetic field (RH) loop test or a current-voltage (IV) curve test.

### Claim 19 (depends on 17)

The method according to claim 17, wherein performing the test comprises performing the test on the transistor using the test node, the word-line, the select-line, and the substrate, and wherein the test comprises a current-voltage (IV) curve test.

### Claim 20 (depends on 17)

The method according to claim 17, wherein performing the test comprises performing the test on both the MTJ and the transistor using the bit-line, the word-line, the select-line, and the substrate, and wherein the test comprises a resistance-magnetic field (RH) loop test, a current-voltage (IV) curve test for the MTJ, or an IV curve test for the transistor.