# US 2013/0155752 A1 · Wiring configuration of a bus system and power wires in a memory chip

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- Number: US 2013/0155752 A1
- Document ID: US20130155752A1
- Status: Published application
- Kind: A1
- Application number: 13/327,057
- Filed: 2011-12-15
- Published: 2013-06-20
- Earliest claimed: 2011-12-15
- Assignees: Elpida Memory, Inc.
- Inventors: Maksim Kuzmenka; Dirk Scheideler; Kai Schiller
- Web page: https://patentgrep.com/patent/US20130155752A1

## CPC

- G11C 7/20: Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 5/148: {Details of power up or power down circuits, standby circuits or recovery circuits}
- G11C 7/18: Bit line organisation; Bit line lay-out
- H03K 19/1776: for memories
- G11C 11/4097: Bit-line organisation, e.g. bit-line layout, folded bit lines
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

Devices and circuits for wiring configurations of a bus system and power supply wires in a memory chip with improved power efficiencies. For example, the effective resistance on the power supply wires can be reduced by utilizing non-active bus wires as additional power wires connected in parallel with the other supply wires. Further, these non-active bus wires can reduce or prevent parasitic couplings and cross-talk effects between neighboring sensitive wires, thereby improving the performance of the chip.

## Claims

### Claim 1

A device comprising:
a signal line extending from a first node to a second node to transfer a signal therethrough;
a power line supplied with a power voltage, the power line extending along the signal line to have third and fourth nodes corresponding respectively to the first and second nodes of the signal line; and
a control circuit configured to form a first electrical path between the first node of the signal line and the third node of the power line and a second electrical path between the second node of the signal line and the fourth node of the power line when the signal is free from being transferred through the signal line.

### Claim 2 (depends on 1)

The device as claimed in claim 1; further comprising:
a first inverter provided at the first node of the signal line to receive the signal and transfer the received signal into the signal line;
a second inverter provided at the second node of the signal line to receive the signal on the signal line; and
a third inverter including an input connected to an output of the second inverter and an output connected to an input of the second inverter.

### Claim 3 (depends on 2)

The device as claimed in claim 2,
wherein the third inverter is a tri-state buffer receiving an enable signal, and the control circuit outputs the enable signal.

### Claim 4 (depends on 1)

The device as claimed in claim 1; further comprising:
a first inverter provided at the first node of the signal line to receive the signal and transfer the received signal into the signal line;
a second inverter provided at the second node of the signal line to receive the signal on the signal line; and
a latch circuit connected to an output of the second inverter,
wherein the first and second inverters are controlled by an enable signal output from the control circuit.

### Claim 5 (depends on 1)

The device as claimed in claim 1, further comprising:
a first inverter provided at the first node of the signal line to receive the signal and transfer the received signal into the signal line;
a second inverter provided at the second node of the signal line to receive the signal on the signal line; and
a first transistor provided between the first node of the signal line and the third node of the power line and controlled by an enable signal; and
a second transistor provided between the second node of the signal line and the fourth node of the power line and controlled by the enable signal,
wherein the control circuit outputs the enable signal.

### Claim 6 (depends on 5)

The device as claimed in claim 5,
wherein the first and second inverter each is a tri-state buffer receiving the enable signal.

### Claim 7 (depends on 1)

The device as claimed in claim 1,
wherein the signal line is a configuration bus.

### Claim 8

A device, comprising:
a first signal line;
a second signal line; and
a control circuit configured to transfer a first data signal on the first signal line and short the second signal line with the power supply line during the first period when not permitting a data to be transferred on the second signal line, the control circuit further being configured to transfer a second data signal on the second signal line during a second period different from the first period.

### Claim 9 (depends on 8)

The device as claimed in claim 8; further comprising:
a first inverter provided at a first node of the second signal line to receive the data and transfer the received data into the second signal line;
a second inverter provided at a second node of the second signal line to receive the data on the second signal line; and
a third inverter including an input connected to an output of the second inverter and an output connected to an input of the second inverter.

### Claim 10 (depends on 9)

The device as claimed in claim 9, wherein the third inverter is a tri-state buffer receiving an enable signal.

### Claim 11 (depends on 8)

The device as claimed in claim 8; further comprising:
a first inverter provided at a first node of the second signal line to receive the data and transfer the received data into the second signal line;
a second inverter provided at a second node of the second signal line to receive the data on the second signal line; and
a latch circuit connected to an output of the second inverter.

### Claim 12 (depends on 8)

The device as claimed in claim 8, further comprising:
a first inverter provided at a first node of the second signal line to receive the data and transfer the received data into the second signal line;
a second inverter provided at a second node of the second signal line to receive the data on the second signal line;
a first transistor provided between the first node of the second signal line and the power source line and controlled by an enable signal; and
a second transistor provided between the second node of the second signal line and the power source line and controlled by the enable signal,
wherein the control circuit outputs the enable signal.

### Claim 13 (depends on 12)

The device as claimed in claim 12, wherein the first and second inverter each is a tri-state buffer receiving the enable signal.

### Claim 14 (depends on 8)

The device as claimed in claim 8, further comprising:
a third signal line;
a fourth signal line; and
a second power supply line supplied with a second power source,
wherein the power supply line is a first power supply line;
wherein the logic circuit configures to transfer a third data signal on the third signal line during the first period, a fourth data signal on the fourth signal line during the second period, the logic circuit further configures to short the fourth signal line with the second power supply line during the first period; and
wherein the first to fourth signal lines are arranged in that order.

### Claim 15 (depends on 8)

The device as claimed in claim 8,
wherein the first signal line is a data bus, and the second signal line is a configuration bus.

### Claim 16

A device comprising:
a first pad for a first power source;
a second pad for a second power source;
a first group of pads;
a second group of pads;
an interface logic connected to the first and second pads, and the first and second groups of the pads;
a memory array;
an array control logic configured to communicate with the memory array;
a first power source line provided between the interface logic and the array control logic to receive the first power source from the first pad;
a second power source line provided between the interface logic and the array control logic to receive the second power source from the second pad;
a plurality of data bus lines provided between the interface logic and the array control logic to transfer data between the first group of pads and the memory array; and
a plurality of configuration bus lines provided between the interface logic and the array control logic to transfer configuration information from the second group of pads to the array control logic,
wherein the interface logic controls to transfer configuration information through the configuration bus lines in a first mode;
wherein the interface logic controls to short a first one of the configuration bus lines with the second power line in a second mode.

### Claim 17 (depends on 16)

The device as claimed in claim 16,
wherein the interface logic controls to short a second one of the configuration bus lines with the first power line in the second mode.

### Claim 18 (depends on 17)

The device as claimed in claim 17,
wherein a first one of the data bus lines, the first one of the configuration bus line, a second one of the data bus lines, and the second one of the configuration bus line are arranged in that order.

### Claim 19 (depends on 16)

The device as claimed in claim 16, further comprising:
a first inverter having an input connected to a first one of the data bus lines and an output connected to a first output node;
a second inverter having an input connected to the first one of the configuration bus lines and an output connected to a second output node; and
a third inverter having an input connected to the second output node and an input connected to the first one of the configuration bus lines,
wherein the first to third inverters are commonly connected to the first and second power source lines.

### Claim 20 (depends on 19)

The device as claimed in claim 19,
wherein the third inverter is controlled by an enable signal.