# US 2013/0155746 A1 · Power layer generation of inverter gate drive signals

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- Number: US 2013/0155746 A1
- Document ID: US20130155746A1
- Status: Published application
- Kind: A1
- Application number: 13/767,732
- Filed: 2013-02-14
- Published: 2013-06-20
- Earliest claimed: 2010-07-16
- Assignees: Rockwell Automation Technologies, Inc.
- Inventors: Alan J. Campbell; Richard H. Radosevich
- Web page: https://patentgrep.com/patent/US20130155746A1

## CPC

- H02M 7/537: using semiconductor devices only, e.g. single switched pulse inverters
- H03K 5/135: by the use of time reference signals, e.g. clock signals
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

Techniques include systems and methods of synchronizing multiple parallel inverters in a power converter system. In one embodiment, control circuitry is connected to a power layer interface circuitry at each of the parallel inverters, via an optical fiber interface. The system is synchronized by transmitting a synchronizing pulse to each of the inverters. Depending on the operational mode of the system, different data exchanges may occur in response to the pulse. In an off mode, power up and power down data may be exchanged between the control circuitry and the inverters. In an initiating mode, identification data may be transmitted from the inverters to the control circuitry. In an active mode, control data may be sent from the control circuitry to the inverters. In some embodiments, the inverters also transmit feedback data and/or acknowledgement signals to the control circuitry. Power layer circuitry of the inverter adjusts a local clock based upon sampled data from the control circuitry to maintain synchronicity of the inverters between synchronization pulses.

## Claims

### Claim 1

A system for controlling operation of power inverter switches, comprising:
control circuitry configured to generate gate timing-related signals for timing of state changes of the switches;
a plurality of inverters coupled to the control circuitry in parallel, the output of the inverters being coupled to provide a common 3-phase output, each inverter comprising power layer circuitry and a plurality of solid state switches coupled to the power layer circuitry; and
a plurality of data conductors, one data conductor coupled between the control circuitry the power layer circuitry of each inverter for conveying the gate timing-related signals from the control circuitry to the respective power layer circuitry;
wherein power layer circuitry of each inverter is configured to receive the gate timing-related signals and to recompute the timing for the state changes based upon the received gate timing-related signals to control state changes of the solid state switches of the respective inverter to convert input power to controlled output power based upon the recomputed timing; and
wherein the control circuitry is configured to periodically transmit synchronization signals to the power layer circuitry of each inverter and the power layer circuitry of each inverter is configured to adjust a respective power layer clock between the synchronization signals to compensate for variability in an operating frequency of an oscillator upon which the power layer clock is based.

### Claim 2 (depends on 1)

The system of claim 1, wherein substantially identical gate timing-related signals are transmitted to the power layer circuitry of all inverters at substantially the same time.

### Claim 3 (depends on 1)

The system of claim 1, wherein the power layer circuitry of each inverter is configured to adjust the respective power layer clock based upon data sampled from the timing-related signals transmitted by the control circuitry.

### Claim 4 (depends on 3)

The system of claim 3, wherein the power layer circuitry of each inverter is configured to adjust the respective power layer clock based upon a number of data bits sampled between transition bits in the sampled data.

### Claim 5 (depends on 1)

The system of claim 1, wherein the power layer circuitry of each inverter is configured to acknowledge receipt of the synchronization signal.

### Claim 6 (depends on 5)

The system of claim 5, wherein in the event of failure of the power layer circuitry of any inverter to acknowledge receipt of the synchronization signal, the control circuitry is configured to command the power layer circuitry of all inverters to operate on the basis of previous gate timing-related signals.

### Claim 7 (depends on 1)

The system of claim 1, wherein the control circuitry is configured to generate a control event signal for synchronizing events in one or more operational modes of the system, and wherein the power layer circuitry of each inverter is configured to receive the control event signal and to communicate with the control circuitry based on the control event signal and based on one of a plurality of operational modes of the system.

### Claim 8

A system for controlling operation of a power inverter, comprising:
control circuitry configured to generate a control event signal for synchronizing events in one or more operational modes of the system;
a data conductor coupled to the control circuitry for conveying the signals to and from the control circuitry;
power layer circuitry coupled to the data conductor and configured to receive the control event signal and to communicate with the control circuitry via the data conductor based on the control event signal and based on the operational mode of the system; and
a plurality of solid state switches coupled to the power layer circuitry and configured to change state to convert input power to controlled output power based on the control event signal and based on the operational mode of the system.

### Claim 9 (depends on 8)

The system of claim 8, wherein the control event signal comprises a sync cycle comprising one rising edge and one falling edge approximately 6 μs following the one rising edge.

### Claim 10 (depends on 8)

The system of claim 8, wherein the data conductor comprises two optical fibers.

### Claim 11 (depends on 10)

The system of claim 10, wherein a first optical fiber is dedicated to transmitting signals from the control circuitry to the power layer circuitry, and a second optical fiber is dedicated to transmitting signals from the power layer circuitry to the control circuitry.

### Claim 12 (depends on 11)

The system of claim 11, wherein the power layer circuitry transmits, over the second optical fiber, at least signals representative of power phase current.

### Claim 13 (depends on 12)

The system of claim 12, wherein the power layer circuitry also transmits, over the second optical fiber, signals representative of at least one of temperature, bus voltage, and fault status.

### Claim 14 (depends on 11)

The system of claim 11, wherein the one or more operational modes comprises an off mode, and wherein the control circuitry is configured to transmit a sync pulse to the power layer circuitry and configured to receive power down data from the power layer circuitry during the off mode.

### Claim 15 (depends on 11)

The system of claim 11, wherein the one or more operational modes comprises an initializing mode, and wherein the control circuitry is configured to transmit a sync pulse to the power layer circuitry and configured to receive identification data from the power layer circuitry during the initializing mode.

### Claim 16 (depends on 15)

The system of claim 15, wherein the control circuitry is further configured to transmit thermal parameter data to the power layer circuitry during the initializing mode.

### Claim 17 (depends on 11)

The system of claim 11, wherein the one or more operational modes comprises an active mode, and wherein the control circuitry transmits a sync pulse and control data to the power layer circuitry during the active mode.

### Claim 18 (depends on 17)

The system of claim 17, wherein the control circuitry receives an acknowledgement signal from the power layer circuitry following the transmitted control data during the active mode.

### Claim 19 (depends on 17)

The system of claim 17, wherein the control circuitry is further configured to transmit thermal parameter data to the power layer circuitry during the active mode.

### Claim 20 (depends on 19)

The system of claim 19, wherein the power layer circuitry is further configured to transmit a thermal feedback signal to the control circuitry in response to the thermal parameter data transmitted from the control circuitry.

### Claim 21 (depends on 17)

The system of claim 17, wherein the control data comprises encoded data and timing information, and wherein the power layer circuitry is configured to recompute timing information from the control data to drive the plurality of solid state switches.