# US 2013/0155636 A1 · Dummy through-silicon via capacitor

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- Number: US 2013/0155636 A1
- Document ID: US20130155636A1
- Status: Published application
- Kind: A1
- Application number: 13/713,667
- Filed: 2012-12-13
- Published: 2013-06-20
- Earliest claimed: 2011-12-16
- Inventors: Changyok Park
- Web page: https://patentgrep.com/patent/US20130155636A1

## CPC

- H10W 70/611: {for connecting multiple chips together}
- H01R 4/00: Electrically-conductive connections between two or more conductive members in direct contact, i.e. touching one another; Means for effecting or maintaining such contact; Electrically-conductive connections having two or more spaced connecting locations for conductors and using contact members penetrating insulation
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/212: {Top-view shapes or dispositions, e.g. top-view layouts of the vias}
- H10W 44/601: {Capacitive arrangements (H10W44/20 takes precedence)}
- H10W 70/635: {Through-vias}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H01R: ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS

## Abstract

An integrated circuit device includes dummy through-silicon vias (TSVs) that can be connected to one or more voltage references, thereby increasing a capacitance associated with the integrated circuit device, such as a decoupling capacitance. In addition, the dummy TSVs can be distributed based on the distribution of active TSVs in the device, thus increasing the stability and performance of the TSV manufacturing process.

## Claims

### Claim 1

A method, comprising:
coupling a first plurality of dummy through-silicon vias (TSVs) of an integrated circuit device to a first voltage reference to set a capacitance associated with the integrated circuit device.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
coupling a second plurality of dummy TSVs of the integrated circuit device to a second voltage reference to set the capacitance.

### Claim 3 (depends on 2)

The method of claim 2, wherein the number of dummy TSVs of the first plurality of dummy TSVs is substantially the same as the number of TSVs of the second plurality of dummy TSVs.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
coupling a substrate of the integrated circuit device to a second voltage reference to set the capacitance, the plurality of dummy TSVs extending through at least a portion of the substrate.

### Claim 5 (depends on 1)

The method of claim 1, further comprising spatially distributing the first plurality of dummy TSVs based on a spatial distribution of a plurality of active TSVs of the integrated circuit device.

### Claim 6 (depends on 5)

The method of claim 5, the first plurality of dummy TSVs having a different depth than the plurality of active TSVs.

### Claim 7 (depends on 5)

The method of claim 5, wherein spatially distributing the plurality of dummy TSVs comprises spatially distributing the plurality of dummy TSVs such that the plurality of dummy TSVs and the plurality of active TSVs are together distributed in a substantially uniform distribution at a substrate of the integrated circuit device.

### Claim 8

A method, comprising forming an integrated circuit device to have a plurality of active TSVs and a plurality of dummy TSVs, and coupling a first subset of the plurality of dummy TSVs to a first voltage reference to set a capacitance associated with the integrated circuit device.

### Claim 9 (depends on 8)

The method of claim 8, further comprising coupling a second subset of the plurality of dummy TSVs to a second voltage reference to set the capacitance.

### Claim 10 (depends on 9)

The method of claim 9, wherein the first subset consists of approximately half of the plurality of dummy TSVs.

### Claim 11 (depends on 10)

The method of claim 10, wherein the second subset consists of approximately half of the plurality of dummy TSVs.

### Claim 12 (depends on 8)

The method of claim 8, further comprising coupling a substrate of the integrated circuit device to a second voltage reference to set the capacitance, the plurality of dummy TSVs extending through at least a portion of the substrate.

### Claim 13 (depends on 8)

The method of claim 8, wherein the plurality of dummy TSVs have a different depth than the plurality of active TSVs.

### Claim 14

An integrated circuit device comprising a plurality of active TSVs and a plurality of dummy TSVs, a first subset of the plurality of dummy TSVs coupled to a first voltage reference to set a capacitance associated with the integrated circuit device.

### Claim 15 (depends on 14)

The integrated circuit device of claim 14, wherein a second subset of the plurality of dummy TSVs is coupled to a second voltage reference to set the capacitance.

### Claim 16 (depends on 14)

The integrated circuit device of claim 14, wherein the first subset consists of approximately half of the plurality of dummy TSVs.

### Claim 17 (depends on 16)

The integrated circuit device of claim 16, wherein the second subset consists of approximately half of the plurality of dummy TSVs.

### Claim 18 (depends on 14)

The integrated circuit device of claim 14, wherein a substrate of the integrated circuit device is coupled to a second voltage reference to set the capacitance, the plurality of dummy TSVs extending through at least a portion of the substrate.

### Claim 19 (depends on 14)

The integrated circuit device of claim 14, wherein the plurality of dummy TSVs have a different depth than the plurality of active TSVs.

### Claim 20 (depends on 14)

The integrated circuit device of claim 14, wherein the capacitance is a decoupling capacitance of the integrated circuit device.