# US 2013/0155629 A1 · Hermetic Semiconductor Package Structure and Method for Manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0155629 A1 - Document ID: US20130155629A1 - Status: Published application - Kind: A1 - Application number: 13/469,052 - Filed: 2012-05-10 - Published: 2013-06-20 - Earliest claimed: 2011-12-19 - Assignees: Tong Hsing Electronic Industries, Ltd. - Inventors: Shao-Pin Ru - Web page: https://patentgrep.com/patent/US20130155629A1 ## CPC - H10W 95/00: Packaging processes not covered by the other groups of this subclass - B81B 7/007: {Interconnections between the MEMS and external electrical signals} - H10W 76/153: having interconnections in passages through the insulating or insulated base - H10W 76/60: Seals - B81B 2207/096: through the substrate - B81C 2203/0109: Bonding an individual cap on the substrate - B81C 2203/019: characterised by the material or arrangement of seals between parts - H10W 70/635: {Through-vias} - H10W 72/884: {Die-attach connectors and bond wires} - Y10T 29/4913: Assembling to base an electrical component, e.g., capacitor, etc. - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - B81B: MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES (piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/00, H10N35/00) - B81C: PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS (making microcapsules or microballoons B01J13/02; processes or apparatus specially adapted for the manufacture or treatment of piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/01) - Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION ## Abstract The invention provides a semiconductor package structure, comprising: a substrate having a first surface and a second surface; a first conductive layer plated on the first surface; a semiconductor element attached to the first conductive layer on the first surface of the substrate for electrically connecting; a second conductive layer plated on the first surface and surrounded the semiconductor element and the first conductive layer, wherein the height of the second conductive layer is higher than the first conductive layer; and a lid attached to the top of the second conductive layer for sealing the semiconductor element. ## Claims ### Claim 1 A semiconductor package structure, comprising: a substrate having a first surface, a second surface and a metal contact penetrating the substrate from the first surface to the second surface; a first conductive layer which is plated on the first surface of the substrate and connected to the metal contact; a semiconductor element electrically connecting the first conductive layer on the first surface of the substrate; a second conductive layer which is plated on the first surface of the substrate surrounding the first conductive layer and the semiconductor element, wherein the height of the second conductive layer is higher than the height of the first conductive layer; and a lid attached to the top of the second conductive layer for sealing the semiconductor element. ### Claim 2 (depends on 1) The semiconductor package structure according to claim 1, wherein the substrate is a ceramic substrate. ### Claim 3 (depends on 1) The semiconductor package structure according to claim 1, further comprising a third conductive layer between the first surface of the substrate and the second conductive layer, wherein the third conductive layer surrounds the first conductive layer. ### Claim 4 (depends on 1) The semiconductor package structure according to claim 1, further comprising a surface finish layer plated on the surface of the first and second conductive layer. ### Claim 5 (depends on 3) The semiconductor package structure according to claim 3, further comprising a surface finish layer plated on the surface of the first conductive layer and second conductive layer and third conductive layer. ### Claim 6 (depends on 1) The semiconductor package structure according to claim 1, wherein the lid is formed by a material selected from a group consisting of metal, alloy, metal composite, plastic, and ceramic materials. ### Claim 7 (depends on 1) The semiconductor package structure according to claim 1, wherein the semiconductor element and the first conductive layer are electrically connected by wires, wherein the wires are comprised of conductive materials. ### Claim 8 (depends on 1) The semiconductor package structure according to claim 1, wherein the semiconductor element and the first conductive layer are electrically connected by bumps, wherein the bumps are comprised of conductive materials. ### Claim 9 (depends on 4) The semiconductor package structure according to claim 4, further comprising a redistribution layer plated on the second surface of the substrate and electrically connecting to the metal contact, wherein the redistribution layer is plated by the surface finish layer. ### Claim 10 (depends on 5) The semiconductor package structure according to claim 5, further comprising a redistribution layer plated on the second surface of the substrate and electrically connecting to the metal contact, wherein the redistribution layer is plated by the surface finish layer. ### Claim 11 (depends on 4) The semiconductor package structure according to claim 4, wherein the surface finish layer is selected from a group consisting of Ag, Au, Ni, Pd, and a combination of those. ### Claim 12 (depends on 5) The semiconductor package structure according to claim 5, wherein the surface finish layer is selected from a group consisting of Ag, Au, Ni, Pd, and a combination of those. ### Claim 13 (depends on 9) The semiconductor package structure according to claim 9, wherein the surface finish layer is selected from a group consisting of Ag, Au, Ni, Pd, and a combination of those. ### Claim 14 (depends on 10) The semiconductor package structure according to claim 10, wherein the surface finish layer is selected from a group consisting of Ag, Au, Ni, Pd, and a combination of those. ### Claim 15 (depends on 2) The semiconductor package structure according to claim 2, wherein the ceramic substrate is a multi-layer ceramic. ### Claim 16 A method for manufacturing semiconductor package structure, comprising the steps of: (a) providing a substrate having a first surface, a second surface and an opening penetrating the substrate from the first surface to the second surface; (b) forming a metal contact in the opening; (c) plating a first conductive layer on the first surface of the substrate, wherein the first conductive layer electrically connects to the metal contact; (d) plating a second conductive layer on the first surface of the substrate for surrounding the semiconductor element and the first conductive layer, wherein the height of the second conductive layer is higher than the first conductive layer; (e) attaching a semiconductor element to the first conductive layer on the first surface of the substrate for electrically connecting; and (f) attaching a lid to the top of the second conductive layer for sealing the semiconductor element. ### Claim 17 (depends on 16) The method for manufacturing semiconductor package structure according to claim 16, wherein the substrate is a ceramic substrate. ### Claim 18 (depends on 16) The method for manufacturing semiconductor package structure according to claim 16, between the step (d) and (e), further comprising a step of plating a surface finish layer on the surfaces of the first and second conductive layer, wherein the surface finish layer is selected from a group consisting of Ag, Au, Ni, Pd, and a combination thereof. ### Claim 19 (depends on 18) The method for manufacturing semiconductor package structure according to claim 18, wherein the surface finish layer is formed by electrochemical deposition. ### Claim 20 (depends on 16) The method for manufacturing semiconductor package structure according to claim 16, wherein the lid is formed by a material selected from a group consisting of metal, alloy, metal composite, plastic, and ceramic materials. ### Claim 21 (depends on 16) The method for manufacturing semiconductor package structure according to claim 16, wherein the semiconductor element electrically connects to the first conductive layer by wire bonding. ### Claim 22 (depends on 16) The method for manufacturing semiconductor package structure according to claim 16, wherein the semiconductor element electrically connects to the first conductive layer by flip chip bonding. ### Claim 23 (depends on 16) The method for manufacturing semiconductor package structure according to claim 16, wherein the step (c) further comprises a step of plating a third conductive layer between the first surface of the substrate and the second conductive layer, the third conductive layer surrounding the semiconductor element and the first conductive layer ### Claim 24 (depends on 16) The method for manufacturing semiconductor package structure according to claim 16, after the step (b), further comprising a step of plating a redistribution layer on the second surface of the substrate for electrically connecting to the metal contact. ### Claim 25 (depends on 23) The method for manufacturing semiconductor package structure according to claim 23, further comprising a step of plating a redistribution layer on the second surface of the substrate for electrically connecting to the metal contact. ### Claim 26 (depends on 16) The method for manufacturing semiconductor package structure according to claim 16, wherein the step (b) and the step (c) take place simultaneously.