# US 2013/0155558 A1 · Compact electronic device for protecting from electrostatic discharge

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- Number: US 2013/0155558 A1
- Document ID: US20130155558A1
- Status: Published application
- Kind: A1
- Application number: 13/705,503
- Filed: 2012-12-05
- Published: 2013-06-20
- Earliest claimed: 2011-12-16
- Assignees: STMicroelectronics S.r.l.
- Inventors: Johan Bourgeat; Philippe Galy
- Web page: https://patentgrep.com/patent/US20130155558A1

## CPC

- H10W 42/60: protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60)
- H02H 9/04: responsive to excess voltage (lightning arrestors H01C7/12, H01C8/04, H01G9/18, H01T)
- H10D 18/80: Bidirectional devices, e.g. triacs
- H10D 89/713: {including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices}
- H10D 89/931: {characterised by the dispositions of the protective arrangements}
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 89/814: {involving a parasitic bipolar transistor triggered by the electrical biasing of the gate electrode of the FET, e.g. gate coupled transistors}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A device for protecting a set of N nodes from electrostatic discharges, wherein N is greater than or equal to three, includes a set of N units respectively possessing N first terminals respectively connected to the N nodes and N second terminals connected together to form a common terminal. Each unit includes at least one MOS transistor including a parasitic transistor connected between a pair of the N nodes and configured, in the presence of a current pulse between the pair of nodes, to operate, at least temporarily, in a hybrid mode including MOS-type operation in a sub-threshold mode and operation of the bipolar transistor.

## Claims

### Claim 1

A device for protecting a set of N nodes from electrostatic discharge, N being three or more, comprising:
a set of N units respectively possessing N first terminals respectively connected to the N nodes and N second terminals connected together to form a common terminal,
wherein each unit comprises at least one MOS transistor including a parasitic transistor connected between two terminals of the MOS transistor and configured, in the presence of a current pulse between the two terminals, to operate, at least temporarily, in a hybrid mode including MOS-type operation in a sub-threshold mode and operation of the bipolar transistor.

### Claim 2 (depends on 1)

The device according to claim 1, wherein the MOS transistor has a first electrode coupled to the first terminal, a second electrode coupled to said common terminal, a gate coupled to a substrate of the MOS transistor without being directly coupled to the first terminal, and a resistive element coupled between the substrate of the MOS transistor and the first terminal.

### Claim 3 (depends on 1)

The device according to claim 1, further comprising a triggerable element possessing at least one control electrode that is connected between each pair of nodes in the set of nodes, the control electrodes of all the triggerable elements being connected to said common terminal.

### Claim 4 (depends on 3)

The device according to claim 3, for protecting three nodes, in which each triggerable element is a triac comprising two fingers, and the six fingers of the three triacs and the three units are integrated into four semiconductor wells.

### Claim 5 (depends on 1)

The device according to claim 1, in which a gate length of each MOS transistor is less than 1 micron.

### Claim 6

A device for protecting a set of N nodes from electrostatic discharge, comprising:
a set of N units respectively possessing N first terminals respectively connected to the N nodes and N second terminals connected together to form a common terminal,
wherein each unit comprises a MOS transistor having a first electrode coupled to the first terminal, a second electrode coupled to said common terminal, a gate coupled to a substrate of the MOS transistor without being directly coupled to the first terminal, and a resistive element coupled between the substrate of the MOS transistor and the first terminal.

### Claim 7 (depends on 6)

The device according to claim 6, further comprising a triggerable element possessing at least one control electrode that is connected between each pair of nodes in the set of nodes, the control electrodes of all the triggerable elements being connected to said common terminal.

### Claim 8 (depends on 7)

The device according to claim 7, for protecting three nodes, in which each triggerable element is a triac comprising two fingers, and the six fingers of the three triacs and the three units are integrated into four semiconductor wells.

### Claim 9 (depends on 6)

The device according to claim 6, in which a gate length of each MOS transistor is less than 1 micron.

### Claim 10

An input/output cell of an integrated circuit, comprising:
an input/output pad,
a first supply terminal,
a second supply terminal, and ‘a circuit configured to protect said input/output pad, the first supply terminal and the second supply terminal, said circuit comprising, connected between each of a pair of nodes selected from the group consisting of the input/output pad, first supply terminal and second supply terminal:
at least one MOS transistor including a parasitic transistor connected between the pair of nodes and configured, in the presence of a current pulse between the pair of nodes, to operate, at least temporarily, in a hybrid mode including MOS-type operation in a sub-threshold mode and operation of the bipolar transistor.

### Claim 11

An ESD circuit, comprising:
a first MOS transistor coupled between a first supply node and a common node, the first MOS transistor having a gate terminal connected to a bulk of the first MOS transistor without a direct connection to said first supply node; and
a second MOS transistor coupled between a second supply node and the common node, the second MOS transistor having a gate terminal connected to a bulk of the second MOS transistor without a direct connection to said second supply node.

### Claim 12 (depends on 11)

The ESD circuit of claim 11, further comprising:
a third MOS transistor coupled between an input-output node and the common node, the third MOS transistor having a gate terminal directly connected to a bulk of the third MOS transistor without a direct connection to said input-output node.

### Claim 13 (depends on 12)

The ESD circuit of claim 12, further comprising a first triac coupled between the input-output node and the first supply node, said first triac having a control terminal coupled to the common node.

### Claim 14 (depends on 12)

The ESD circuit of claim 12, further comprising a second triac coupled between the input-output node and the second supply node, said second triac having a control terminal coupled to the common node.

### Claim 15 (depends on 12)

The ESD circuit of claim 12, further comprising a third triac coupled between the first supply node and the second supply node, said third triac having a control terminal coupled to the common node.

### Claim 16 (depends on 11)

The ESD circuit of claim 11, wherein the gate terminal and bulk of the first MOS transistor are indirectly connected to said first supply node through a resistor.

### Claim 17 (depends on 11)

The ESD circuit of claim 11, wherein the gate terminal and bulk of the first MOS transistor are indirectly connected to said first supply node through a series connection of a resistor and diode.

### Claim 18 (depends on 11)

The ESD circuit of claim 11, wherein the gate terminal is directly connected to the bulk of the first MOS transistor.

### Claim 19 (depends on 11)

The ESD circuit of claim 11, wherein the gate terminal is connected to the bulk of the first MOS transistor through a diode.

### Claim 20 (depends on 11)

The ESD circuit of claim 11, wherein the gate terminal is connected to the bulk of the first MOS transistor through a source-drain path of an additional MOS transistor, wherein a gate of the additional MOS transistor is directly connected to a bulk of the additional MOS transistor.