# US 2013/0155279 A1 · Apparatus, methods and systems for randomly accessing pixel data from streaming image sensor data > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0155279 A1 - Document ID: US20130155279A1 - Status: Published application - Kind: A1 - Application number: 13/328,503 - Filed: 2011-12-16 - Published: 2013-06-20 - Earliest claimed: 2011-12-16 - Assignees: University of Saskatchewan - Inventors: Tareq Hasan Khan; Khan Arif Wahid - Web page: https://patentgrep.com/patent/US20130155279A1 ## CPC - H04N 25/00: Circuitry of solid-state image sensors [SSIS]; Control thereof - H04N 25/76: Addressed sensors, e.g. MOS or CMOS sensors - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract Apparatus, methods and systems for bridging between commercially available, high-speed image sensors and low cost, low power microcontrollers. An image sensor interface processor is provided for controlling an image sensor, and receiving and storing image data. A microcontroller (or other general purpose or image processor) can communicate with the image sensor interface processor, to access pixel data in a random access fashion through a parallel memory access interface at any speed desired by the microcontroller. Moreover, automatic power management of the image sensor can be provided by the image sensor interface processor. In some alternative embodiments, the described image sensor interface processor may be integrated into the image sensor itself, or a microcontroller, or some other intermediate device. ## Claims ### Claim 1 An interface processor for providing random access to an image frame from an image sensor, the processor comprising: a memory; a sensor control module configured to transmit a wake signal to the image sensor; a pixel stream module configured to receive a data signal at an output data rate from the image sensor following transmission of the wake signal and store the data signal in the memory, wherein the data signal comprises a plurality of pixels that correspond to the image frame; and a frame access module configured to receive an address signal, determine a selected pixel of the plurality of pixels referenced by the address signal, retrieve the selected pixel from the memory, and transmit an image signal comprising the selected pixel. ### Claim 2 (depends on 1) The processor of claim 1, wherein the data signal is received from the image sensor in real-time. ### Claim 3 (depends on 2) The processor of claim 2, wherein the data signal is received using a DVP interface. ### Claim 4 (depends on 1) The processor of claim 1, wherein the sensor control module is further configured to transmit a configuration command to the image sensor. ### Claim 5 (depends on 4) The processor of claim 4, wherein the configuration command comprises a frame size or color depth. ### Claim 6 (depends on 4) The processor of claim 4, wherein the configuration command is a sleep command, and wherein the sleep command is transmitted following receipt of the plurality of pixels that correspond to the image frame. ### Claim 7 (depends on 4) The processor of claim 4, wherein the configuration command uses the I2C protocol. ### Claim 8 (depends on 1) The processor of claim 1, wherein the sensor control module is further configured to store a configuration mapping associated with the image sensor, and wherein the configuration mapping comprises one or more register addresses and one or more register entries for controlling the image sensor. ### Claim 9 (depends on 8) The processor of claim 8, wherein the sensor control module is further configured to receive the configuration mapping prior to transmitting the wake signal. ### Claim 10 (depends on 1) The processor of claim 1, wherein the plurality of pixels are transmitted serially in the data signal. ### Claim 11 (depends on 1) The processor of claim 1, wherein the plurality of pixels are transmitted serially on a row-by-row basis in the data signal. ### Claim 12 (depends on 1) The processor of claim 1, wherein the selected pixel is individually addressable in the plurality of pixels. ### Claim 13 (depends on 1) The processor of claim 1, wherein the selected pixel is determined based on a row and a column of the image frame provided in the address signal. ### Claim 14 (depends on 13) The processor of claim 13, further comprising an address generation module configured to generate a read address for the selected pixel based on the row and the column provided in the address signal. ### Claim 15 (depends on 1) The processor of claim 1, wherein the image signal is transmitted to a microcontroller. ### Claim 16 (depends on 15) The processor of claim 15, wherein an input data rate of the microcontroller is lower than the output data rate of the data signal. ### Claim 17 (depends on 1) The processor of claim 1, wherein the frame access module is further configured to receive a block size signal, determine a block of pixels in the plurality of pixels referenced by the address signal and the block size signal, retrieve the block of pixels from the memory, and transmit the image signal comprising the block of pixels, and wherein the block of pixels comprises the selected pixel. ### Claim 18 A method for providing random access to an image frame from an image sensor, the method comprising: transmitting a wake signal to the image sensor from an interface processor; receiving a data signal at an output data rate from the image sensor following transmission of the wake signal; storing the data signal in a memory, wherein the data signal comprises a plurality of pixels that correspond to the image frame; receiving an address signal; determining a selected pixel of the plurality of pixels referenced by the address signal; retrieve the selected pixel from the memory; and transmitting an image signal comprising the selected pixel. ### Claim 19 An image sensing system, the system comprising: an image sensor; a processor; and an interface processor for providing random access to an image frame from the image sensor, the interface processor comprising: a memory; a sensor control module configured to transmit a wake signal to the image sensor; a pixel stream module configured to receive a data signal at an output data rate from the image sensor following transmission of the wake signal and store the data signal in the memory, wherein the data signal comprises a plurality of pixels that correspond to the image frame; and a frame access module configured to receive an address signal, determine a selected pixel of the plurality of pixels referenced by the address signal, retrieve the selected pixel from the memory, and transmit an image signal comprising the selected pixel.