# US 2013/0155082 A1 · Data stream processing architecture enabling extension of neighborhood mask

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- Number: US 2013/0155082 A1
- Document ID: US20130155082A1
- Status: Published application
- Kind: A1
- Application number: 13/637,366
- Filed: 2011-03-17
- Published: 2013-06-20
- Earliest claimed: 2010-03-26
- Assignees: Commissariat A L'energie Atomique Et Aux Energies Alternatives
- Inventors: Maria Lecellier; Stéphane Guyetant; Renaud Schmit
- Web page: https://patentgrep.com/patent/US20130155082A1

## CPC

- G06T 1/00: General purpose image data processing
- G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL

## Abstract

An architecture for processing a data stream forming matrices of pixels of dimension Nl×Nc. The processing architecture includes processing units and interconnection means making it possible to transfer the data stream between them. Each processing unit includes a control unit, neighborhood processors capable of carrying out the instructions from the control unit and a neighborhood storage unit enabling each neighborhood processor to access a neighborhood of dimension Vl×Vc. The invention makes it possible to extend the dimension of the neighborhoods accessible to the neighborhood processors by a coupling of two or more processing units. To this end, the architecture includes a storage manager enabling the neighborhood processors of the coupled processing units to access adjoining neighborhoods of pixels, and means for communication between neighborhood processors allowing for an exchange of data relating to the different neighborhoods.

## Claims

### Claim 1

A data stream processing architecture, the data forming matrices of pixels of dimension Nl×Nc, the architecture comprising:
processing units, each processing unit being capable of receiving an input data stream and of delivering an output data stream, and each processing unit comprising:
a control unit capable of supplying instructions,
a set of neighborhood processors capable of performing the instructions received from the control unit and of supplying data forming the output data stream of the processing unit, and
a neighborhood storage unit enabling each neighborhood processor to access data of the input data stream received by the processing unit forming a neighborhood of pixels of dimension Vl×Vc, the neighborhoods accessible to the processors being centered on contiguous pixels of one and the same row of a matrix, two processors being neighbors when the neighborhoods that they can access are centered on contiguous pixels in one and the same row of a matrix; and
interconnection means capable of receiving a data stream at an input of the architecture and the output data streams of the processing units, and capable of delivering a data stream at an output of the architecture, wherein
two processing units can be coupled on a North/South axis and each comprise:
one and the same number N of neighborhood processors; and
intra-unit connection means enabling each neighborhood processor to exchange data with each of its neighboring processors, so that the neighborhood of pixels accessible to a neighborhood processor can be extended to all the neighborhoods of pixels accessible to the neighborhood processors of the coupled processing unit concerned, said set forming a neighborhood of pixels of dimension Vl×(Vc+N−1); and
the architecture further comprises:
a storage manager capable of receiving a data stream from the interconnection means and enabling the neighborhood processors of a first coupled processing unit to access neighborhoods of pixels contiguous with the neighborhoods of pixels accessible to the neighborhood processors of a second coupled processing unit, so that the neighborhoods of pixels accessible to the neighborhood processors of the two coupled processing units can form a vicinity of dimension 2·Vl×(Vc+N−1); and
connection means on the North/South axis enabling each neighborhood processor of the first coupled processing unite to exchange data with one of the neighborhood processors of the second coupled processing unit, the neighborhood processors being linked in pairs so as to have access to neighborhoods of pixels centered on one and the same column of a matrix, so that the neighborhood of pixels accessible to each neighborhood processor can be extended to the neighborhoods of pixels accessible to the neighborhood processor to which it is linked.

### Claim 2 (depends on 1)

The architecture as claimed in claim 1, wherein the storage manager comprises:
a reserve memory for each coupled processing unit on the North/South axis, each reserve memory being capable of storing data from the stream received by the processing unit considered being able to form a global neighborhood of pixels of dimension Vl×Nc, the neighborhood storage unit of each coupled processing unit enabling each of its neighborhood processors to access data in the reserve memory associated with the coupled processing unit considered; and
connection means between the reserve memories, so that the reserve memories associated with two coupled processing units can store data that can form a coupled neighborhood of pixels of maximum dimension 2·Vl×Nc.

### Claim 3 (depends on 2)

The architecture as claimed in claim 2, in which wherein the reserve memories each comprise Vl memory rows, each memory row being capable of storing data from a row of a matrix, the memory rows being linked in series, so that a data stream stored on a first memory row can be transmitted successively to the other memory rows.

### Claim 4 (depends on 3)

The architecture as claimed in claim 3, wherein the connection means between two reserve memories comprise a multiplexer with Vl inputs and one output, each input being able to be linked to one of the memory rows of a first reserve memory, the output being able to be linked to an input of the second reserve memory.

### Claim 5 (depends on 1)

The architecture as claimed in claim 1, wherein
two processing units can be coupled on an East/West axis; and
the architecture further comprises connection means on the East/West axis enabling a neighborhood processor of a first processing unit coupled on the East/West axis to exchange data with a neighboring neighborhood processor of a second processing unit coupled on the East/West axis to the first processing unit, so that the neighborhood of pixels accessible to each of said neighborhood processors is formed by the joining of the neighborhoods of pixels accessible to each of the two neighborhood processors.

### Claim 6 (depends on 5)

The architecture as claimed in claim 5, in which the storage manager comprises:
a reserve memory for each processing unit coupled on the East/West axis, each reserve memory being capable of storing data from the stream received by the processing unit considered being able to form a global neighborhood of pixels of dimension Vl×Nc, the neighborhood storage unit of each coupled processing unit enabling each of its neighborhood processors to access data from the reserve memory associated with the coupled processing unit considered; and
connection means between the reserve memories, so that the reserve memories associated with two processing units coupled on the East/West axis can store data that can form a coupled neighborhood of pixels of maximum dimension Vl×2·Nc.

### Claim 7 (depends on 1)

The architecture as claimed in claim 1, further comprising means for synchronizing the coupled processing units to check that the data that have to be recovered by the neighborhood processors of a first processing unit have been made available by the neighborhood processors of a second processing unit coupled with the first processing unit.

### Claim 8 (depends on 7)

The architecture as claimed in claim 7, wherein the synchronization means of the coupled processing units comprise a flag for each coupling between two processing units, each flag being able to indicate either that the data that have to be recovered by the neighborhood processors of a first processing unit have been made available by the neighborhood processors of a second processing unit coupled with the first processing unit, or that said data are not available.

### Claim 9 (depends on 1)

The architecture as claimed in claim 1, wherein each neighborhood storage unit comprises a memory making it possible to store the data forming the neighborhoods of pixels which the neighborhood processors can access.

### Claim 10 (depends on 1)

The architecture as claimed in claim 1, wherein the connection means on the North/South axis comprise, for each neighborhood processor of a processing unit coupled on the North/South axis, a data register accessible to the neighborhood processor to which it is linked.

### Claim 11 (depends on 1)

The architecture as claimed in claim 1, wherein the intra-unit connection means and, where appropriate, the connection means on the East/West axis, comprise, for each neighborhood processor, a first data register accessible to one of its neighboring neighborhood processors, and a second data register accessible to its other neighboring neighborhood processor.

### Claim 12 (depends on 1)

The architecture as claimed in claim 1, comprising K·M processing units organized in a matrix of K processing units coupled in pairs on the North/South axis and M processing units coupled in pairs on the East/West axis, the storage manager being configured so that the reserve memories can store data that can form a coupled neighborhood of dimension K·Vl×M·Nc, and the connection means being configured so that the neighborhood of pixels accessible to each neighborhood processor of a coupled processing unit can be extended to the neighborhoods of pixels accessible to the neighborhood processors of the coupled processing units.