# US 2013/0155077 A1 · Policies for Shader Resource Allocation in a Shader Core

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- Number: US 2013/0155077 A1
- Document ID: US20130155077A1
- Status: Published application
- Kind: A1
- Application number: 13/325,286
- Filed: 2011-12-14
- Published: 2013-06-20
- Earliest claimed: 2011-12-14
- Assignees: Advanced Micro Devices, Inc.
- Inventors: Robert Scott HARTOG; Mark Leather; Michael Mantor; Rex McCrary; Sebastien Nussbaum; Philip J. Rogers; Ralph Clay Taylor; Thomas Woller
- Web page: https://patentgrep.com/patent/US20130155077A1

## CPC

- G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues}
- G06F 9/3851: {from multiple instruction streams, e.g. multistreaming}
- G06F 9/3879: {for non-native instruction execution, e.g. executing a command; for Java instruction set}
- G06F 9/3888: {controlled by a single instruction for multiple threads [SIMT] in parallel}
- G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL

## Abstract

A method of determining priority within an accelerated processing device is provided. The accelerated processing device includes compute pipeline queues that are processed in accordance with predetermined criteria. The queues are selected based on priority characteristics and the selected queue is processed until a time quantum lapses or a queue having a higher priority becomes available for processing.

## Claims

### Claim 1

A method of determining priority within an accelerated processing device (APD) including compute pipelines, comprising:
selecting a first queue and a second queue from the compute pipeline processing queues within each of the compute pipelines in accordance with predetermined criteria; and
selecting one of the first and second queues for processing in accordance with priority criteria;
wherein the selected queue is processed until at least one from the group including (i) lapse of a time quantum and (ii) a queue having a higher priority becomes available.

### Claim 2 (depends on 1)

The method of claim 1, wherein processing the selected queue comprises preempting the selected queue.

### Claim 3 (depends on 2)

The method of claim 2, wherein preempting the selected queue comprises performing a context switching operation on the selected queue.

### Claim 4 (depends on 2)

The method of claim 2, further comprising initiating processing of a second queue after the preempting.

### Claim 5 (depends on 1)

The method of claim 1, further comprising determining a relative priority of each of the compute pipelines.

### Claim 6 (depends on 5)

The method of claim 5, wherein the relative priority of each of the compute pipelines is determined using a least recently issued circuit.

### Claim 7 (depends on 6)

The method of claim 6, wherein the least recently issued circuit is a totem pole circuit.

### Claim 8 (depends on 6)

The method of claim 6, further comprising assigning the compute pipeline having the lowest priority to the bottom the circuit.

### Claim 9 (depends on 1)

The method of claim 1, wherein the first queue is a ready queue.

### Claim 10 (depends on 1)

The method of claim 1, wherein the second queue is an active queue.

### Claim 11 (depends on 1)

The method of claim 1, wherein the predetermined criteria include (i) a queue priority, (ii) a queue quantum duration, and (iii) a queue ready control.

### Claim 12

A system, comprising:
a memory; and
an accelerated processing device (APD) including compute pipelines coupled to the memory, wherein the compute pipelines are configured to, based on an instruction stored in memory,
select a first queue and a second queue from compute pipeline processing queues within each of the compute pipelines in accordance with predetermined criteria;
select one of the first and second queues for processing in accordance with priority criteria; and
process the selected queue until at least one from the group including (i) lapse of a time quanta and (ii) a queue having a higher priority becomes available.

### Claim 13 (depends on 12)

The system of claim 12, wherein the compute pipelines are configured to preempt processing the selected queue.

### Claim 14 (depends on 13)

The system of claim 13, wherein the compute pipelines are configured to context the selected queue during the preempting.

### Claim 15 (depends on 13)

The system of claim 13, wherein the compute pipelines are configured to initiate processing of a second queue after the preempting.

### Claim 16 (depends on 12)

The system of claim 12, further comprising a shader input block coupled to the compute pipelines and configured to determine a relative priority of each of the compute pipelines.

### Claim 17 (depends on 16)

The system of claim 16, wherein the relative priority of each of the compute pipelines is determined using a least recently issued circuit.

### Claim 18 (depends on 17)

The system of claim 17, wherein the least recently issued circuit is a totem pole circuit.

### Claim 19 (depends on 17)

The system of claim 17, further comprising assigning the compute pipeline having the lowest priority to the bottom of the circuit.

### Claim 20 (depends on 12)

The method of claim 12, wherein the first queue is a ready queue.

### Claim 21 (depends on 12)

The method of claim 12, wherein the second queue is an active queue.

### Claim 22 (depends on 12)

The method of claim 12, wherein the predetermined criteria include (i) a queue priority, (ii) a queue quantum duration, and (iii) a queue ready control.