# US 2013/0155046 A1 · Level Shifter With Low Voltage Loss

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- Number: US 2013/0155046 A1
- Document ID: US20130155046A1
- Status: Published application
- Kind: A1
- Application number: 13/689,534
- Filed: 2012-11-29
- Published: 2013-06-20
- Earliest claimed: 2011-12-20
- Assignees: Parade Technologies, Ltd.
- Inventors: Liang Xu; Hongquan Wang
- Web page: https://patentgrep.com/patent/US20130155046A1

## CPC

- H04N 5/66: Transforming electric information into light information (scanning details H04N3/00)
- G09G 5/006: {Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04)}
- H03K 19/018507: {Interface arrangements}
- G09G 2310/0289: Details of voltage level shifters arranged for use in a driving circuit
- G09G 2370/047: using display data channel standard [DDC] communication
- G09G 2370/10: Use of a protocol of communication by packets in interfaces along the display data pipeline
- G09G 2370/12: Use of DVI or HDMI protocol in interfaces along the display data pipeline
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A system and method are disclosed for level shifting a DDC bus with a low voltage loss. A pull up circuit includes an NMOS transistor, a PMOS transistor and resistor. An NMOS pull up gate is also included in line with the DDC bus. When powered, the level shifter adjusts the voltage of transmitted signals to match the voltage of a receiving device. The resulting adjusted is slightly lower due to a threshold voltage lost across one or more transistors. Additionally, when unpowered, the level shifter releases the signal transmission line. Unadjusted signals can then be transmitted without consumption of power by the level shifter.

## Claims

### Claim 1

A method for level shifting a display data channel with low voltage loss, the method comprising:
receiving a first signal from a first video interface, the first video interface operating at a high voltage level, the first signal at the high voltage level; reducing the voltage of the first signal to better match the voltage of a second video interface, the second video interface operating at a low voltage level, the low voltage level between zero and the high voltage level; and
transmitting the first signal with a reduced voltage level to the second video interface.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
receiving a second signal from the second video interface, the second signal having a voltage level matching the low voltage level of the second video interface;
increasing the voltage level of the second signal to better match voltage level of the first video interface; and
transmitting the second signal with an increased voltage level to the first video interface.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
receiving a third signal from the first video interface, the third signal having a voltage level of zero; and
transmitting the third signal to the second video interface with little modification to the voltage level.

### Claim 4 (depends on 3)

The method of claim 3, further comprising:
receiving a fourth signal from the second video interface, the fourth signal having a voltage level of zero; and
transmitting the fourth signal to the first video interface with little modification to the voltage level.

### Claim 5 (depends on 1)

The method of claim 1, wherein the first video interface is HDMI or DVI.

### Claim 6 (depends on 5)

The method of claim 5, wherein the second video interface is DISPLAYPORT.

### Claim 7 (depends on 1)

The method of claim 1, wherein the first signal is transmitted the second video interface with an unadjusted voltage level if circuitry to reduce the voltage level of the first signal is unpowered.

### Claim 8 (depends on 3)

The method of claim 3, wherein the third signal is transmitted to the second video interface without a power source.

### Claim 9

An apparatus for level shifting with low voltage loss, the apparatus comprising:
a display data channel coupled to a source operating at a first voltage level and a sink operating at a second voltage level;
an NMOS pass gate in line with the display data channel and coupled to the sink; and
a pull up circuit coupled to the display data channel between the source and the NMOS pass gate, the pull up circuit comprising an NMOS transistor, a PMOS transistor and a first resistor between the NMOS transistor and PMOS transistor, wherein the PMOS transistor is coupled to a first voltage source at the first voltage level.

### Claim 10 (depends on 9)

The apparatus of claim 9, further comprising:
a pull-up resistor circuit coupled to the sink, the pull-up resistor circuit comprising a second resistor coupled to a second voltage source at the second voltage level.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein the source is a DISPLAYPORT video interface.

### Claim 12 (depends on 10)

The apparatus of claim 10, wherein the sink is an HDMI or DVI video interface.

### Claim 13 (depends on 10)

The apparatus of claim 10, wherein the first voltage source is unpowered and the display data channel is capable of transmitting a logic 1 or 0.

### Claim 14 (depends on 10)

The apparatus of claim 10, wherein the NMOS transistor and the PMOS transistor include parasitic diodes.

### Claim 15

An apparatus for level shifting with low voltage loss, the apparatus comprising:
a means for receiving a first signal from a first video interface, the first video interface operating at a high voltage level, the first signal at the high voltage level;
a means for reducing the voltage of the first signal to better match the voltage of a second video interface, the second video interface operating at a low voltage level, the low voltage level between zero and the high voltage level; and
a means for transmitting the first signal with a reduced voltage level to the second video interface.

### Claim 16 (depends on 15)

The apparatus of claim 15, further comprising:
a means for receiving a second signal from the second video interface, the second signal having a voltage level matching the low voltage level of the second video interface;
a means for increasing the voltage level of the second signal to better match voltage level of the first video interface; and
a means for transmitting the second signal with an increased voltage level to the first video interface.

### Claim 17 (depends on 16)

The apparatus of claim 16, further comprising:
a means for receiving a third signal from the first video interface, the third signal having a voltage level of zero; and
a means for transmitting the third signal to the second video interface with little modification to the voltage level.

### Claim 18 (depends on 17)

The apparatus of claim 17, further comprising:
a means for receiving a fourth signal from the second video interface, the fourth signal having a voltage level of zero; and
a means for transmitting the fourth signal to the first video interface with little modification to the voltage level.

### Claim 19 (depends on 15)

The apparatus of claim 15, wherein the first signal is transmitted the second video interface with an unadjusted voltage level if circuitry to reduce the voltage level of the first signal is unpowered.

### Claim 20 (depends on 17)

The apparatus of claim 17, wherein the third signal is transmitted to the second video interface without a power source.
