# US 2013/0155035 A1 · Method for driving pixel circuits

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- Number: US 2013/0155035 A1
- Document ID: US20130155035A1
- Status: Published application
- Kind: A1
- Application number: 13/609,310
- Filed: 2012-09-11
- Published: 2013-06-20
- Earliest claimed: 2011-12-16
- Assignees: Au Optronics Corporation
- Inventors: Szu-Chieh CHEN; Yu-Hsin TING; Chung-Lung LI; Chen-Ming CHEN; I-Fang CHEN; Yun-Chung LIN; Da-Yei FAN; Yi-Xuan HUNG; Chun-Yu HUANG
- Web page: https://patentgrep.com/patent/US20130155035A1

## CPC

- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- G09G 3/2003: {Display of colours (specific for liquid crystal displays G09G3/3607)}
- G09G 2310/0251: Precharge or discharge of pixel before applying new pixel voltage
- G09G 2310/0254: Control of polarity reversal in general, other than for liquid crystal displays
- G09G 2310/067: Special waveforms for scanning, where no circuit details of the gate driver are given
- G09G 2320/0209: Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

A method for driving a pixel circuit, which is adapted to drive a first pixel circuit coupled to a first gate line and a second pixel circuit coupled to a second gate line, is disclosed. The first pixel circuit receives display data before the second pixel circuit does. The method provides only one first enable pulse to the first gate line in a frame, and provides a second enable pulse and a third enable pulse to the second gate line in the same frame. The starting time of the second enable pulse is in an enabled time period of the first enable pulse, and the enabled time period of the third enable pulse is after the enabled time periods of the first and second enable pulses.

## Claims

### Claim 1

A method for driving pixel circuits, adapted for driving a first pixel circuit controlled by a first gate line for receiving data and a second pixel circuit controlled by a second gate line for receiving data, wherein the first pixel circuit receives a display data for displaying earlier than the second pixel circuit, and the method comprises:
only providing one first enabling pulse to the first gate line in a frame; and
providing a second enabling pulse and a third enabling pulse to the second gate line in the frame,
wherein an enabling start-up time of the second enabling pulse is in an enabling time period of the first enabling pulse, and an enabling time period of the third enabling pulse is behind the enabling time period of the first enabling pulse and an enabling time period of the second enabling pulse.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the first gate line is configured adjacent to the second gate line.

### Claim 3 (depends on 2)

The method according to claim 2, wherein the data polarity variations of the first pixel circuit and the second pixel circuit are matched to two-dot inversion or row inversion operation mode.

### Claim 4 (depends on 1)

The method according to claim 1, wherein after providing the first enabling pulse to the first gate line, other three gate lines are enabled before providing the third enabling pulse to the second gate line.

### Claim 5 (depends on 4)

The method according to claim 4, wherein the data polarity variations of the first pixel circuit and the second pixel circuit are matched to one of dot inversion, two-dot inversion, column inversion and row inversion operation modes.

### Claim 6 (depends on 1)

The method according to claim 1, further employing a third gate line to control a third pixel circuit for receiving data and employing a fourth gate line to control a fourth pixel circuit for receiving data, wherein the third pixel circuit receives the display data for displaying earlier than the fourth pixel circuit, and the method further comprises:
providing a fourth enabling pulse and a fifth enabling pulse to the third gate line in the frame; and
providing a sixth enabling pulse, a seventh enabling pulse and an eighth enabling pulse to the fourth gate line in the frame,
wherein an enabling start-up time of the fourth enabling pulse is in the enabling time period of the first enabling pulse, an enabling time period of the fifth enabling pulse is behind the enabling time period of the third enabling pulse, an enabling start-up time of the sixth enabling pulse is in the enabling time period of the third enabling pulse, an enabling start-up time of the seventh enabling pulse is in the enabling time period of the fifth enabling pulse, and an enabling time period of the eighth enabling pulse is behind the enabling time period of the fifth enabling pulse.

### Claim 7 (depends on 6)

The method according to claim 6, wherein the first gate line is configured adjacent to the second gate line.

### Claim 8 (depends on 6)

The method according to claim 6, wherein the third gate line is disposed adjacent to the fourth gate line.

### Claim 9 (depends on 6)

The method according to claim 6, wherein the data polarity variations of the first, the second, the third and the fourth pixel circuits are matched to one of two-dot inversion and row inversion operation modes.

### Claim 10 (depends on 1)

The method according to claim 1, further employing a third gate line to control whether or not a third pixel circuit receives data and a fourth gate line to control whether or not a fourth pixel circuit receives data, wherein the third pixel receives the display data for displaying earlier than the fourth pixel circuit, and the method further comprises:
providing a fourth enabling pulse and a fifth enabling pulse to the third gate line in the frame; and
providing a sixth enabling pulse, a seventh pulse and an eighth enabling pulse to the fourth gate line in the frame,
wherein an enabling start-up time of the fourth enabling pulse is in the enabling time period of the first enabling pulse, an enabling time period of the fifth enabling pulse is behind the enabling time period of the first enabling pulse, an enabling start-up time of the sixth enabling pulse is in the enabling time period of the fifth enabling pulse, an enabling start-up time of the seventh enabling pulse is in the enabling time period of the third enabling pulse, and an enabling time period of the eighth enabling pulse is behind the enabling time period of the third enabling pulse.

### Claim 11 (depends on 10)

The method according to claim 10, wherein the first gate line is disposed adjacent to the third gate line.

### Claim 12 (depends on 10)

The method according to claim 10, wherein the second gate line is disposed adjacent to the fourth gate line.

### Claim 13 (depends on 10)

The method according to claim 10, wherein the data polarity variations of the first, the second, the third and the fourth pixel circuits are matched to one of two-dot inversion and row inversion operation modes.

### Claim 14 (depends on 1)

The method according to claim 1, further comprising performing the method in a previous frame and a next frame of the frame.