# US 2013/0154909 A1 · Semiconductor device, display panel and electronic apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0154909 A1 - Document ID: US20130154909A1 - Status: Published application - Kind: A1 - Application number: 13/755,824 - Filed: 2013-01-31 - Published: 2013-06-20 - Earliest claimed: 2008-05-03 - Assignees: Sony Corporation - Inventors: Seiichiro Jinta - Web page: https://patentgrep.com/patent/US20130154909A1 ## CPC - G09G 3/3258: with pixel circuitry controlling the voltage across the light-emitting element - G09G 3/3208: organic, e.g. using organic light-emitting diodes [OLED] - G09G 3/3266: Details of drivers for scan electrodes - G09G 5/18: Timing circuits for raster scan displays (specially adapted for television H04N {; synchronisation between the display unit and other display units, videodisc player G09G5/12}) - H03K 3/012: Modifications of generator to improve response time or to decrease power consumption - G09G 3/2011: {by amplitude modulation} - G09G 3/3426: {the different display panel areas being distributed in two dimensions, e.g. matrix} - G09G 2300/0417: Special arrangements specific to the use of low carrier mobility technology - G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes - G09G 2310/0251: Precharge or discharge of pixel before applying new pixel voltage - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2330/021: Power management, e.g. power saving - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A semiconductor device includes a plurality of thin film transistors of a single channel formed on an insulating substrate, and a buffer circuit including an outputting stage; a first inputting stage; a second inputting stage; a seventh thin film transistor; and an eighth thin film transistor. ## Claims ### Claim 1 A semiconductor device, comprising a plurality of thin film transistors of a single channel formed on an insulating substrate, and a buffer circuit including: an outputting stage formed from a series connection of first and second thin film transistors and having an output terminal at a node between said first and second thin film transistors; a first inputting stage formed from a series connection of a third thin film transistor for being controlled with a set pulse and a fourth thin film transistor for being controlled with a reset pulse and configured to switchably control a potential state of a first controlling wiring line connected to a control electrode of said first thin film transistor between a potential state within a period from an application starting timing of the set pulse to an application starting timing of the reset pulse and another potential state within any other period through a potential appearing at a node between said third and fourth thin film transistors; a second inputting stage formed from a series connection of a fifth thin film transistor for being controlled with the reset pulse and a sixth thin film transistor for being controlled with the set pulse and configured to switchably control a potential state of a second controlling wiring line connected to a control electrode of said second thin film transistor in a phase relationship reverse to that of a potential variation of said first controlling wiring line through a potential appearing at a node between said fifth and sixth thin film transistors; a seventh thin film transistor connected at one of main electrodes thereof to said first controlling wiring line and at the other main electrode thereof to a power supply common to said second, fourth and sixth thin film transistors and further connected at a control electrode thereof to said second controlling wiring line; and an eighth thin film transistor connected at one of main electrodes thereof to said second controlling wiring line and at the other main electrode thereof to the power supply common to said second, fourth and sixth thin film transistors and further connected at a control electrode thereof to said first controlling wiring line. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the set pulse and the reset pulse have an amplitude smaller than that of an output pulse appearing at said output terminal. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein each of the set pulse and the reset pulse is supplied from a corresponding shift register circuit. ### Claim 4 (depends on 3) The semiconductor device according to claim 3, wherein the output pulse of said buffer circuit is used for control of a current supplying line of a display panel. ### Claim 5 (depends on 4) The semiconductor device according to claim 4, wherein the output pulse of said buffer circuit is used for lighting control of the display panel of a self luminous type, and the period from the application starting timing of the set pulse to the application starting timing of the reset pulse provides any light emitting period length disposed within a one-field period. ### Claim 6 (depends on 5) The semiconductor device according to claim 5, wherein said third and fifth thin film transistors are connected in diode connection. ### Claim 7 (depends on 6) The semiconductor device according to claim 6, wherein said first thin film transistor receives, at one of main electrodes thereof, a pulse signal for causing a plurality of output pulses to be generated within the period from the application starting timing of the set pulse to the application starting timing of the reset pulse. ### Claim 8 (depends on 7) The semiconductor device according to claim 7, wherein the output pulse of said buffer circuit is used for control of a sampling timing of the display panel. ### Claim 9 A semiconductor device, comprising a plurality of thin film transistors of a single channel formed on an insulating substrate, and a buffer circuit including: an outputting stage formed from a series connection of first and second thin film transistors and having an output terminal at a node between said first and second thin film transistors; a first inputting stage formed from a series connection of a third thin film transistor for being controlled with a set pulse and a fourth thin film transistor for being controlled with a reset pulse and configured to switchably control a potential state of a first controlling wiring line connected to a control electrode of said first thin film transistor between a potential state within a period from an application starting timing of the set pulse to an application starting timing of the reset pulse and another potential state within any other period through a potential appearing at a node between said third and fourth thin film transistors; a second inputting stage formed from a series connection of a fifth thin film transistor for being controlled with the reset pulse and a sixth thin film transistor for being controlled with the set pulse and configured to switchably control a potential state of a second controlling wiring line connected to a control electrode of said second thin film transistor in a phase relationship reverse to that of a potential variation of said first controlling wiring line through a potential appearing at a node between said fifth and sixth thin film transistors; and a seventh thin film transistor connected at one of main electrodes thereof to said first controlling wiring line and at the other main electrode thereof to a power supply common to said second, fourth and sixth thin film transistors and further connected at a control electrode thereof to said second controlling wiring line. ### Claim 10 A semiconductor device, comprising a plurality of thin film transistors of a single channel formed on an insulating substrate, and a buffer circuit including: an outputting stage formed from a series connection of first and second thin film transistors and having an output terminal at a node between said first and second thin film transistors; a first inputting stage formed from a series connection of a third thin film transistor for being controlled with a set pulse and a fourth thin film transistor for being controlled with a reset pulse and configured to switchably control a potential state of a first controlling wiring line connected to a control electrode of said first thin film transistor between a potential state within a period from an application starting timing of the set pulse to an application starting timing of the reset pulse and another potential state within any other period through a potential appearing at a node between said third and fourth thin film transistors; a second inputting stage formed from a series connection of a fifth thin film transistor for being controlled with the reset pulse and a sixth thin film transistor for being controlled with the set pulse and configured to switchably control a potential state of a second controlling wiring line connected to a control electrode of said second thin film transistor in a phase relationship reverse to that of a potential variation of said first controlling wiring line through a potential appearing at a node between said fifth and sixth thin film transistors; and an eighth thin film transistor connected at one of main electrodes thereof to said second controlling wiring line and at the other main electrode thereof to a power supply common to said second, fourth and sixth thin film transistors and further connected at a control electrode thereof to said first controlling wiring line. ### Claim 11 A display panel, comprising: a pixel array section formed from a plurality of thin film transistors of a single channel on an insulating substrate; and a buffer circuit of a driving circuit configured to drive and control said pixel array section, said buffer circuit including an outputting stage formed from a series connection of first and second thin film transistors and having an output terminal at a node between said first and second thin film transistors, a first inputting stage formed from a series connection of a third thin film transistor for being controlled with a set pulse and a fourth thin film transistor for being controlled with a reset pulse and configured to switchably control a potential state of a first controlling wiring line connected to a control electrode of said first thin film transistor between a potential state within a period from an application starting timing of the set pulse to an application starting timing of the reset pulse and another potential state within any other period through a potential appearing at a node between said third and fourth thin film transistors, a second inputting stage formed from a series connection of a fifth thin film transistor for being controlled with the reset pulse and a sixth thin film transistor for being controlled with the set pulse and configured to switchably control a potential state of a second controlling wiring line connected to a control electrode of said second thin film transistor in a phase relationship reverse to that of a potential variation of said first controlling wiring line through a potential appearing at a node between said fifth and sixth thin film transistors, a seventh thin film transistor connected at one of main electrodes thereof to said first controlling wiring line and at the other main electrode thereof to a power supply common to said second, fourth and sixth thin film transistors and further connected at a control electrode thereof to said second controlling wiring line, and an eighth thin film transistor connected at one of main electrodes thereof to said second controlling wiring line and at the other main electrode thereof to the power supply common to said second, fourth and sixth thin film transistors and further connected at a control electrode thereof to said first controlling wiring line. ### Claim 12 An electronic apparatus, comprising: a pixel array section formed from a plurality of thin film transistors of a single channel on an insulating substrate; a buffer circuit of a driving circuit configured to drive and control said pixel array section, said buffer circuit including an outputting stage formed from a series connection of first and second thin film transistors and having an output terminal at a node between said first and second thin film transistors, a first inputting stage formed from a series connection of a third thin film transistor for being controlled with a set pulse and a fourth thin film transistor for being controlled with a reset pulse and configured to switchably control a potential state of a first controlling wiring line connected to a control electrode of said first thin film transistor between a potential state within a period from an application starting timing of the set pulse to an application starting timing of the reset pulse and another potential state within any other period through a potential appearing at a node between said third and fourth thin film transistors, a second inputting stage formed from a series connection of a fifth thin film transistor for being controlled with the reset pulse and a sixth thin film transistor for being controlled with the set pulse and configured to switchably control a potential state of a second controlling wiring line connected to a control electrode of said second thin film transistor in a phase relationship reverse to that of a potential variation of said first controlling wiring line through a potential appearing at a node between said fifth and sixth thin film transistors, a seventh thin film transistor connected at one of main electrodes thereof to said first controlling wiring line and at the other main electrode thereof to a power supply common to said second, fourth and sixth thin film transistors and further connected at a control electrode thereof to said second controlling wiring line, and an eighth thin film transistor connected at one of main electrodes thereof to said second controlling wiring line and at the other main electrode thereof to the power supply common to said second, fourth and sixth thin film transistors and further connected at a control electrode thereof to said first controlling wiring line; a system control section configured to control operation of said entire system; and an operation inputting section configured to input to said system control section.