# US 2013/0154860 A1 · Use of logic circuit embedded into comparator for foreground offset cancellation

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- Number: US 2013/0154860 A1
- Document ID: US20130154860A1
- Status: Published application
- Kind: A1
- Application number: 13/330,939
- Filed: 2011-12-20
- Published: 2013-06-20
- Earliest claimed: 2011-12-20
- Assignees: Analog Devices, Inc.
- Inventors: Robert Schell; Michael R. Elliott
- Web page: https://patentgrep.com/patent/US20130154860A1

## CPC

- H03M 1/1061: {using digitally programmable trimming circuits}
- H03M 1/167: {all stages comprising simultaneous converters (H03M1/165 takes precedence)}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A system and method are described herein that provide for the calibration of the offset of a comparator on a per-comparator basis. An injection is made to the comparator at determined injection points using a low-power DAC, to calibrate the offset of the comparator. The DAC can be selectively controlled by a digital codeword that is generated based on an output of the comparator and the comparator's offset. Further embodiments of the invention present a system and method for calibrating the offset of a comparator of a flash ADC in each stage of a pipeline ADC. The system and method may provide for the calibration in a manner without affecting the speed of the pipeline ADC or adding significant power to the pipeline ADC.

## Claims

### Claim 1

A system for cancelling an offset of a comparator, the system comprising:
the comparator, wherein input terminals to the comparator are switched to a reference signal;
a logic circuit receiving an output from the comparator and generating a digital codeword; and
a digital to analog converter (“DAC”) that receives that digital codeword and injects a calibration current or voltage or voltage at designated injection points in the comparator to cancel the offset.

### Claim 2 (depends on 1)

The system according to claim 1, wherein the logic circuit and the DAC are implemented locally with the comparator.

### Claim 3 (depends on 1)

The system according to claim 1, wherein the logic circuit stores the generated digital codeword.

### Claim 4 (depends on 1)

The system according to claim 1, wherein the logic circuit is controlled by a calibration signal.

### Claim 5 (depends on 1)

The system according to claim 1, wherein the input terminals to the comparator are switched to the reference signal when input switches are overridden to not switch between an input signal and the reference signal.

### Claim 6 (depends on 1)

The system according to claim 1, wherein the logic circuit is successive approximation recursively (“SAR”) logic or other type of logic controlling the DAC in a similar manner.

### Claim 7 (depends on 2)

The system according to claim 2, wherein the comparator is implemented in an analog to digital converter (“ADC”).

### Claim 8 (depends on 2)

The system according to claim 2, wherein the comparator is implemented in a flash analog to digital converter (“ADC”).

### Claim 9 (depends on 4)

The system according to claim 4, wherein the input terminals to the comparator are switched to the reference signal when the calibration signal goes high.

### Claim 10 (depends on 8)

The system according to claim 8, wherein the flash ADC is incorporated in a stage of a pipeline ADC.

### Claim 11

A method for cancelling an offset of a comparator, the method comprising:
switching input terminals to the comparator to a reference signal for a normal clock cycle;
receiving an output from the comparator by a logic circuit;
generating a digital codeword by the logic circuit;
storing the digital codeword in the logic circuit;
transmitting the digital codeword to a digital to analog converter (“DAC”); and
injecting a calibration current or voltage into the comparator from the DAC at designated injection points to cancel the offset.

### Claim 12 (depends on 11)

The method according to claim 11, wherein the logic circuit and the DAC are implemented locally with the comparator.

### Claim 13 (depends on 11)

The method according to claim 11, wherein the logic circuit is controlled by a calibration signal.

### Claim 14 (depends on 11)

The method according to claim 11, wherein the input terminals to the comparator are switched to the reference signal when input switches are overridden to not switch between an input signal and the reference signal.

### Claim 15 (depends on 11)

The method according to claim 11, wherein the comparator is implemented in an analog to digital converter (“ADC”).

### Claim 16 (depends on 11)

The method according to claim 11, wherein the comparator is implemented in a flash analog to digital converter (“ADC”).

### Claim 17 (depends on 13)

The method according to claim 13, wherein the input terminals to the comparator are switched to the reference signal when the calibration signal goes high.

### Claim 18 (depends on 16)

The method according to claim 16, wherein the flash ADC is incorporated in a stage of a pipeline ADC.