# US 2013/0154741 A1 · Apparatus and circuit for amplifying baseband signal

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- Number: US 2013/0154741 A1
- Document ID: US20130154741A1
- Status: Published application
- Kind: A1
- Application number: 13/715,537
- Filed: 2012-12-14
- Published: 2013-06-20
- Earliest claimed: 2011-12-16
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Jong-Woo LEE; Si-Bum JUN
- Web page: https://patentgrep.com/patent/US20130154741A1

## CPC

- H03F 3/45071: {with semiconductor devices only}
- H03F 1/342: {in field-effect transistor amplifiers}
- H03F 3/195: in integrated circuits
- H03F 3/45179: {using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence)}
- H03F 3/45475: {using IC blocks as the active amplifying circuit}
- H03F 3/45654: {Controlling the active amplifying circuit of the differential amplifier}
- H03F 3/45977: {using switching means, e.g. sample and hold}
- H03L 7/00: Automatic control of frequency or phase; Synchronisation
- H03F 2200/294: the amplifier being a low noise amplifier [LNA]
- H03F 2200/336: A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
- H03F 2200/405: the output amplifying stage of an amplifier comprising more than three power stages
- H03F 2200/451: the amplifier being a radio frequency amplifier
- H03F 2203/45138: Two or more differential amplifiers in IC-block form are combined, e.g. measuring amplifiers
- H03F 2203/45404: the CMCL comprising capacitors containing, not in parallel with the resistors, an addition circuit
- H03F 2203/45421: the CMCL comprising a switched capacitor addition circuit
- H03F 2203/45422: the CMCL comprising one or more capacitors not as integrating capacitor, e.g. for stability purposes
- H03F 2203/45444: the CMCL comprising a sample and hold circuit
- H03F 2203/45512: the FBC comprising one or more capacitors, not being switched capacitors, and being coupled between the LC and the IC
- H03F 2203/45514: the FBC comprising one or more switched capacitors, and being coupled between the LC and the IC
- H03F 2203/45522: the FBC comprising one or more potentiometers
- H03F 2203/45526: the FBC comprising a resistor-capacitor combination and being coupled between the LC and the IC
- H03F 2203/45528: the FBC comprising one or more passive resistors and being coupled between the LC and the IC
- H03F 2203/45591: the IC comprising one or more potentiometers
- H03F 2203/45594: the IC comprising one or more resistors, which are not biasing resistor
- H03F: AMPLIFIERS
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

An operational amplifier circuit is provided. The operational amplifier circuit includes a differential amplifier of a cascade structure and a switched-capacitor type Common-Mode FeedBack (CMFB) circuit. The differential amplifier amplifies a difference between two input signals to output an anode output voltage and a negative output voltage. The switched-capacitor type CMFB circuit averages the anode output voltage and the negative output voltage of the differential amplifier, compares the average voltage with a reference voltage to generate a feedback signal based on a result of the comparison, and provides the feedback signal to the differential amplifier. Therefore, power consumption is reduced and a battery use time of a wireless terminal can be extended. Also, since an operational amplifier gain of each analog filter terminal is not negatively affected, a Direct Current (DC) offset is reduced, thereby improving signal quality.

## Claims

### Claim 1

An operational amplifier circuit, the operational amplifier circuit comprising:
a differential amplifier of a cascade structure, for amplifying a difference between two input signals to output an anode output voltage and a cathode output voltage; and
a switched-capacitor type Common-Mode FeedBack (CMFB) circuit for averaging the anode output voltage and the cathode output voltage of the differential amplifier, for comparing the average voltage with a reference voltage to generate a feedback signal based on a result of the comparison, and for providing the feedback signal to the differential amplifier.

### Claim 2 (depends on 1)

The operational amplifier circuit of claim 1, wherein the CMFB circuit comprises:
a first transistor and a second transistor for switching depending on a first clock;
a first capacitor for being charged with a positive output voltage of the differential operational amplifier depending on the first clock;
a third transistor and a fourth transistor for switching depending on a second clock; and
a second capacitor for being charged with a voltage corresponding to a difference between an ideal output common voltage and an ideal input bias voltage while the voltage charging the first capacitor is discharged depending on the second clock.

### Claim 3 (depends on 2)

The operational amplifier circuit of claim 2, wherein, when the first clock is turned on, the second clock is turned off, and when the first clock is turned off, the second clock is turned on.

### Claim 4 (depends on 2)

The operational amplifier circuit of claim 2, wherein a source of the first transistor and a drain of the second transistor are connected,
wherein a drain of the third transistor and a source of the fourth transistor are connected,
wherein the first capacitor is connected between the source of the first transistor and the drain of the third transistor, and
wherein the second capacitor is connected between the drain of the second transistor and the source of the fourth transistor.

### Claim 5 (depends on 2)

The operational amplifier circuit of claim 2, wherein the first clock is supplied to gates of the second transistor and the fourth transistor, and the second clock is supplied to gates of the first transistor and the third transistor.

### Claim 6 (depends on 1)

The operational amplifier circuit of claim 1, wherein the CMFB circuit comprises:
a first transistor and a second transistor for switching depending on a first clock;
a first capacitor for being charged with a negative output voltage of the differential operational amplifier depending on the first clock;
a third transistor and a fourth transistor for switching depending on a second clock; and
a second capacitor for being charged with a voltage corresponding to a difference between an ideal output common voltage and an ideal input bias voltage while the voltage charging the first capacitor is discharged depending on the second clock.

### Claim 7 (depends on 6)

The operational amplifier circuit of claim 6, wherein, when the first clock is turned on, the second clock is turned off, and when the first clock is turned off, the second clock is turned on.

### Claim 8 (depends on 6)

The operational amplifier circuit of claim 6, wherein a drain of the first transistor and a drain of the second transistor are connected,
wherein a source of the third transistor and a drain of the fourth transistor are connected,
wherein the first capacitor is connected between the drain of the first transistor and the source of the third transistor, and
wherein the second capacitor is connected between the drain of the second transistor and the drain of the fourth transistor.

### Claim 9 (depends on 6)

The operational amplifier circuit of claim 6, wherein the first clock is supplied to gates of the first transistor and the third transistor, and the second clock is supplied to gates of the second transistor and the fourth transistor.

### Claim 10 (depends on 1)

The operational amplifier circuit of claim 1, further comprising:
a clock generator for synchronizing a clock for driving the switched capacitor type CMFB circuit with a sampling clock of an Analog-to-Digital Converter (ADC).

### Claim 11 (depends on 10)

The operational amplifier circuit of claim 10, wherein the sampling clock of the ADC is generated by dividing a local oscillator clock by an integer.

### Claim 12 (depends on 1)

The operational amplifier circuit of claim 1, wherein a common voltage of the differential amplifier is controlled and maintained constant depending on the feedback signal of the CMFB circuit.

### Claim 13

A receiver comprising:
an analog baseband unit for amplifying a baseband signal;
an Analog-to-Digital Converter (ADC) for converting a signal from the analog baseband unit into a digital signal; and
a clock generator for providing a synchronized clock for driving the analog baseband unit and the ADC.

### Claim 14 (depends on 13)

The receiver of claim 13, wherein the analog baseband unit comprises a plurality of analog filter terminals coupled with each other,
wherein each analog filter terminal comprises an operational amplifier, a variable resistor, and a variable capacitor, and
wherein the operational amplifier comprises:
a differential amplifier of a cascade structure, for amplifying and outputting a difference between two signals; and
a switched-capacitor type Common-Mode FeedBack (CMFB) circuit for averaging an anode output voltage and a cathode output voltage of the differential amplifier, for comparing the average voltage with a reference voltage to generate a feedback signal based on a result of the comparison, and for providing a feedback signal to the differential amplifier.

### Claim 15 (depends on 14)

The receiver of claim 14, wherein the CMFB circuit comprises:
a first transistor and a second transistor for switching depending on a first clock;
a first capacitor for being charged with one of a positive and a negative output voltage of the differential operational amplifier depending on the first clock;
a third transistor and a fourth transistor for switching depending on a second clock; and
a second capacitor for being charged with a voltage corresponding to a difference between an ideal output common voltage and an ideal input bias voltage while the voltage charging the first capacitor is discharged depending on the second clock.

### Claim 16 (depends on 15)

The receiver of claim 15, wherein when the first clock is turned on, the second clock is turned off, and when the first clock is turned off, the second clock is turned on.

### Claim 17 (depends on 15)

The receiver of claim 15, wherein a source of the first transistor and a drain of the second transistor are connected,
wherein a drain of the third transistor and a source of the fourth transistor are connected,
wherein the first capacitor is connected between the source of the first transistor and the drain of the third transistor, and
wherein the second capacitor is connected between the drain of the second transistor and the source of the fourth transistor.

### Claim 18 (depends on 17)

The receiver of claim 17, wherein the first clock is supplied to gates of the second transistor and the fourth transistor, and the second clock is supplied to gates of the first transistor and the third transistor.

### Claim 19 (depends on 13)

The receiver of claim 13, further comprising:
a baseband modem for demodulating a digital signal from the ADC as an information signal according to a communication scheme.

### Claim 20 (depends on 13)

The receiver of claim 13, wherein the sampling clock of the ADC is generated by dividing a local oscillator clock by an integer.