# US 2013/0154737 A1 · Comparator and amplifier > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0154737 A1 - Document ID: US20130154737A1 - Status: Published application - Kind: A1 - Application number: 13/612,789 - Filed: 2012-09-12 - Published: 2013-06-20 - Earliest claimed: 2011-11-03 - Assignees: Mediatek Inc. - Inventors: Yun-Shiang SHU - Web page: https://patentgrep.com/patent/US20130154737A1 ## CPC - H03K 5/2481: {with at least one differential stage} - H03F 3/45: Differential amplifiers (differential sense amplifiers G11C7/062) - H03F 3/45071: {with semiconductor devices only} - H03F 3/45179: {using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence)} - H03F 3/45197: {Pl types (H03F3/45224, H03F3/45251 take precedence)} - H03K 5/2472: {using field effect transistors (H03K5/2436 takes precedence)} - H03K 5/249: {using clock signals} - H03F 2203/45424: the CMCL comprising a comparator circuit - H03F 2203/45466: the CSC being controlled, e.g. by a signal derived from a non specified place in the dif amp circuit - H03F 2203/45482: the CSC comprising offset means - H03F 2203/45492: the CSC being a pi circuit and the resistor being implemented by one or more controlled transistors - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H03F: AMPLIFIERS ## Abstract A comparator has a differential pair circuit, a current control circuit, and a latch. The differential pair circuit has first and second comparator transistors, and is arranged to compare a first input and a second input according to a clock signal to generate a result indicating whether a difference of the first and second inputs exceeds an internal offset. The current control circuit is coupled in series with the differential pair circuit, and configured to provide unequal abilities of drawing currents for the first and second comparator transistors. ## Claims ### Claim 1 A comparator, comprising: a differential pair circuit, comprising first and second comparator transistors, configured to compare a first input and a second input according to a clock signal to generate a result indicating whether a difference of the first and second inputs exceeds an internal offset; and a current control circuit, coupled in series with the differential pair circuit, configured to provide unequal abilities of drawing currents for the first and second comparator transistors, respectively. ### Claim 2 (depends on 1) The comparator of claim 1, wherein the internal offset varies with a difference between the unequal abilities of drawing currents. ### Claim 3 (depends on 1) The comparator of claim 1, wherein the current control circuit comprises first, second, and third resistors, and the third resistor is coupled between the first and second resistors, and the first, second, and third resistors are adaptable to change the abilities of drawing currents for the first and second comparator transistors. ### Claim 4 (depends on 1) The comparator of claim 1, wherein the current control circuit comprises first and second transistors having different device sizes and configured by digital control signals. ### Claim 5 (depends on 1) The comparator of claim 1, wherein the current control circuit comprises first and second arrays of transistors, which have different numbers of transistors configured by digital control signals. ### Claim 6 (depends on 1) The comparator of claim 1, further comprises a reset circuit coupled between the current control circuit and a voltage supply, capable of setting a reference voltage point in the differential pair circuit to a predetermined voltage level. ### Claim 7 (depends on 6) The comparator of claim 6, wherein the reset circuit comprises a transistor connected in a diode configuration for resetting the differential pair circuit by the predetermined voltage level. ### Claim 8 (depends on 1) The comparator of claim 1, wherein the differential pair circuit compares the first and second inputs when the clock signal is at a first logic level, and is reset to a predetermined value when the clock signal is at a second logic level. ### Claim 9 (depends on 1) The comparator of claim 1, wherein the differential pair circuit is arranged to compare the first and second inputs by determining a polarity of a difference of the first input and the second input in combination with the internal offset. ### Claim 10 An amplifier, comprising: a differential pair circuit, comprising first and second comparator transistors, configured to compare a first input and a second input when a clock signal is at a first logic level to generate a result indicating whether a difference of the first and second inputs exceeds an internal offset; a current control circuit (tail circuit), configured to provide unequal abilities of drawing currents for the first and second comparator transistors respectively; an amplification circuit, amplifying the generated result from the differential pair circuit; and a reset circuit, capable of setting a reference voltage point in the differential pair circuit to a predetermined voltage level when the clock signal is at a second logic level. ### Claim 11 (depends on 10) The amplifier of claim 10, wherein the internal offset varies with a difference between the unequal abilities of drawing currents. ### Claim 12 (depends on 10) The amplifier of claim 10, wherein the current control circuit is coupled in series to the differential pair circuit. ### Claim 13 (depends on 10) The amplifier of claim 10, wherein the current control circuit comprises first, second, and third resistors, the third resistor is coupled between the first and second resistors, and the first, second, and third resistors are adaptable to change the abilities of drawing currents for the first and second comparator transistors. ### Claim 14 (depends on 10) The amplifier of claim 10, wherein the current control circuit comprises first and second transistors having different device sizes and configured by digital control signals. ### Claim 15 (depends on 10) The amplifier of claim 10, wherein the current control circuit comprises first and second arrays of transistors, which have different numbers of transistors configured by digital control signals. ### Claim 16 (depends on 10) The amplifier of claim 10, wherein the reset circuit is coupled between the current control circuit and a voltage supply. ### Claim 17 (depends on 10) The amplifier of claim 10, wherein the reset circuit comprises a transistor connected in a diode configuration for resetting the differential pair circuit by the predetermined voltage level. ### Claim 18 (depends on 10) The amplifier of claim 10, wherein the differential pair circuit compares the first and second inputs by determining a polarity of a difference of the first input and the second input in combination with the internal offset.