# US 2013/0154727 A1 · Distributed resonant clock grid synthesis

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- Number: US 2013/0154727 A1
- Document ID: US20130154727A1
- Status: Published application
- Kind: A1
- Application number: 13/531,531
- Filed: 2012-06-23
- Published: 2013-06-20
- Earliest claimed: 2011-06-29
- Assignees: The Regents of the University of California Office of Technology Transfer
- Inventors: Matthew Guthaus
- Web page: https://patentgrep.com/patent/US20130154727A1

## CPC

- H10W 90/00: Package configurations
- G06F 1/10: Distribution of clock signals {, e.g. skew}
- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- G06F 30/396: Clock trees
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method of implementing a VLSI clock network is implemented. That method includes a step of generating an initial VLSI clock grid for incorporation on a silicon die. An input grid buffer is then sized and implemented for the VLSI clock grid. LC tanks are then placed and sized in the VLSI clock grid to implement a resonant tank clock grid and the input grid buffer is resized. A check of the resonant tank design criteria is then made. If the design criteria are met the resonant VLSI clock grid with its LC tanks is implemented. If not, another attempt at implementing a suitable LC tanks placement and sizing is made. The process iterates until a VLSI clock grid that meets the design criteria is obtained.

## Claims

### Claim 1

A method of designing VLSI clock distribution networks, comprising the steps of:
(a) obtaining a set of clock distribution network design criteria;
(b) laying out an initial clock grid network;
(c) implementing and sizing input buffers;
(d) placing and implementing LC tanks to resonate with said clock grid network laid out in step (b);
(e) resizing the input buffers in view of LC tanks placed in step (d) based on the results of an AC analysis;
(f) checking whether the clock distribution network design criteria are met when using the resized input buffers;
(g) if the clock distribution network design criteria are met in step (f), implementing a VLSI clock distribution network using the clock grid network, resized input buffers, and placed and implemented LC tanks; and
(h) if the clock distribution network design criteria are not met in step (f), looping back to step (d).

### Claim 2 (depends on 1)

The method of claim 1, wherein step (e) is implemented using an AC-based sizing formulation.

### Claim 3 (depends on 2)

The method of claim 2, further including a step (i) of attaching a DC bias capacitance to each LC tank.

### Claim 4 (depends on 2)

The method of claim 2, wherein step (d) includes sizing each LC tank using a driver resistance of a clock driver.

### Claim 5 (depends on 1)

The method of claim 1, wherein step (a) includes slew and skew constraints.

### Claim 6 (depends on 5)

The method of claim 5, wherein step (a) includes inductor size constraints for each inductor determined by:
cost
n
=
α
×
L
n
L
avg
+
(
1
-
α
)
×
S_LC
avg
S_LC
min
n
wherein Ln is the inductance of LC tank n, S_LCavg is the average resistance from sink to its nearest LC tank, and S_LCmmin is, the minimum resistance from sink to LC tank n.

### Claim 7 (depends on 1)

The method of claim 1, wherein step (d) includes performing the following Pseudo-code algorithm:
Input: Grid nodes N; L is an inductor, resonant frequency f0; maximum inductor area Amax and skew constraint SK.
Output: Inductors size and location L
Input: Grid nodes N; resonant frequency f0; maximum inductor area Amax; skew constraint SK.
Output: Inductors size and location L
1:
L←N
2:
L_sizing( )
4:
while ΣArea(L) > Amax && skew < SK do
5:
for each li ∈ L do
6:
cost
i
=
α
×
l
i
L
avg
+
(
1
-
α
)
×
S_LC
avg
S_LC
min
n
7:
end for
8:
sort_cost(cost)
9:
remove_lc (10% of L with largest cost)
10:
L_sizing( )
11:
if ΣArea(L) < 1.2 Amax then
12:
AC_buf_sizing( )
13:
timing_power_analysis( )
14:
end if
15:
end while

### Claim 8 (depends on 7)

The method of claim 7, wherein step (d) includes performing for an inductor L the following Pseudo-code algorithm for inductor sizing L_sizing( ):
Input: Grid nodes N; inductors L; resonant frequency f0
Output: Sizes for each inductor L
1:
Cn←Σ(wire_cap, buf_cap, sink_cap) connected to n, n ∈ N
2:
CR = 0 // Cap, resonates with each inductor
3:
for each n ∈ N do
4:
Find inductor li, which is resistively closest to n, l ∈ L
5:
CRi += Cn
6:
end for
7:
l
i
=
1
(
2

π

f
0
)
×
CR
i

### Claim 9 (depends on 2)

The method of claim 2, wherein step (e) includes performing the following pseudo-code algorithm:
Require: Clock grid with LC tanks; buffers B; maximum/minimum buffer size bmax/bmin
Ensure: ∀vs≧Vswing, s ∈ S
1:
bcur − (bmin + bmax)/2
2:
set_buf_size (b = bcur,b ε B)
3:
L_sizing( )
4:
while (bmax − bmin) > 0.1 do
5:
AC_analysis( )
6:
if vmin = MIN(vs,s ε S) < Vswing, then
7:
bmin = bcur
8:
else
9:
bmax = bcur
10:
end if
11:
bcur = (bmin + bmax)/2
12:
set_buf_size (bi = bcur,bi ε B)
13.
L_sizing( )
14:
end while

### Claim 10

A system for designing VLSI clock distribution networks, including:
a computer for inputting a set of clock distribution network design criteria;
a computer for laying out an initial clock grid network design by first implementing and sizing input buffers for the clock grid network and then by placing and implementing LC tanks to resonate with the clock grid network;
a computer for simulating the clock grid network by resizing the input buffers in view of the placed and implemented LC tanks based on an AC analysis;
a computer for simulating whether the clock distribution network design criteria are met when using the resized input buffers;
a computer for implementing a resonant grid using the resized input buffers, clock grid, and LC tank placements and implementations if the clock distribution network design criteria are met; and
looping back to placing and implementing LC tanks if the clock distribution network design criteria are not met.

### Claim 11 (depends on 10)

The system of claim 10, wherein the computer resizes the input buffers using an AC-based sizing formulation.

### Claim 12 (depends on 11)

The system of claim 11, wherein the computer for laying out an initial clock grid network further attaches a DC bias capacitance to each LC tank.

### Claim 13 (depends on 11)

The system of claim 11, wherein placing and implementing LC tanks includes sizing each LC tank based on a driver resistance of a clock driver.

### Claim 14 (depends on 10)

The system of claim 10, wherein the input clock distribution network design criteria includes slew and skew constraints.

### Claim 15 (depends on 14)

The system of claim 14, wherein said clock distribution network design criteria includes inductor size constraints for each inductor:
cost
n
=
α
×
L
n
L
avg
+
(
1
-
α
)
×
S_LC
avg
S_LC
min
n
wherein Ln is the inductance of LC tank n, S_LCavg is the average resistance from sink to its nearest LC tank, and S_LCmmin is the minimum resistance from sink to LC tank n.

### Claim 16 (depends on 10)

The system of claim 10, wherein the computer placing and implementing LC tanks does so in accord with the following Pseudo-code algorithm:
Input: Grid nodes N; resonant frequency f0; maximum inductor area Amax; skew constraint SK.
Output: Inductors size and location L
1:
L←N
2:
L_sizing( )
4:
while ΣArea(L) > Amax && skew < SK do
5:
for each li ∈ L do
6:
cost
i
=
α
×
l
i
L
avg
+
(
1
-
α
)
×
S_LC
avg
S_LC
min
n
7:
end for
8:
sort_cost(cost)
9:
remove_lc (10% of L with largest cost)
10:
L_sizing( )
11:
if ΣArea(L) < 1.2 Amax then
12:
AC_buf_sizing( )
13:
timing_power_analysis( )
14:
end if
15:
end while

### Claim 17 (depends on 16)

The system of claim 16, the computer placing and implementing LC tanks performs for inductor L the following Pseudo-code algorithm:
Input: Grid nodes N; inductors L; resonant frequency f0
Output: Sizes for each inductor L
1:
Cn←Σ(wire_cap, buf_cap, sink_cap) connected to n, n ∈ N
2:
CR = 0// Cap, resonates with each inductor
3:
for each n ∈ N do
4:
Find inductor li, which is resistively closest to n, l ∈ L
5:
CRi += Cn
6:
end for
7:
l
i
=
1
(
2

π

f
0
)
×
CR
i

### Claim 18 (depends on 10)

The system of claim 10, wherein the computer resizing the input buffers performs the following pseudo-code algorithm:
Require: Clock grid with LC tanks; buffers B; maximum/minimum buffer size bmax/bmin
Ensure: ∀vs≧Vswing, s ∈ S
1:
bcur − (bmin + bmax)/2
2:
set_buf_size (b = bcur,b ε B)
3:
L_sizing( )
4:
while (bmax − bmin) > 0.1 do
5:
AC_analysis( )
6:
if vmin = MIN(vs,s ε S) < Vswing, then
7:
bmin = bcur
8:
else
9:
bmax = bcur
10:
end if
11:
bcur = (bmin + bmax)/2
12:
set_buf_size (bi = bcur,bi ε B)
13.
L_sizing( )
14:
end while

### Claim 19

A semiconductor device having a clock grid, comprising:
a clock grid conductor;
a set of input buffers driving signals onto the clock grid conductor; and
a set of resonant LC tanks located on the clock grid;
wherein the clock grid conductor, input buffers, and LC tanks are implementations of a design comprised of:
obtaining a set of clock distribution network design criteria;
laying out an initial clock grid network;
implementing and sizing input buffers;
placing and implementing LC tanks to resonate with the clock grid network;
resizing the input buffers in view of LC tanks based on the results of an AC analysis;
checking whether the clock distribution network design criteria are met when using the resized input buffers;
if the clock distribution network design criteria are met then implementing a VLSI clock distribution network using the clock grid network, resized input buffers, and placed and implemented LC tanks; and
if the clock distribution network design criteria are not met looping back to placing and implementing LC tanks to resonate with the clock grid network.

### Claim 20 (depends on 19)

The semiconductor device according to claim 19, wherein the wherein the implementations of the clock grid conductor, the input buffers, and the LC tanks include fabricating a wafer mask derived from the design.