# US 2013/0154724 A1 · Interleaved noise reduction circuit and method

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- Number: US 2013/0154724 A1
- Document ID: US20130154724A1
- Status: Published application
- Kind: A1
- Application number: 13/330,670
- Filed: 2011-12-19
- Published: 2013-06-20
- Earliest claimed: 2011-12-19
- Assignees: Semiconductor Components Industries, LLC
- Inventors: Robert B. Smith; Stan Latimer; Morgan Ercanbrack
- Web page: https://patentgrep.com/patent/US20130154724A1

## CPC

- H03K 5/159: Applications of delay lines not covered by the preceding subgroups
- G01S 7/4876: {by removing unwanted signals (G01S7/495 takes precedence)}
- G01S 17/08: for measuring distance only (indirect measurement G01S17/46; active triangulation systems G01S17/48)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G01S: RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES

## Abstract

In accordance with an embodiment, a noise reduction circuit includes one or more phase sampling circuits that receive an electromagnetic signal and splits the signal into an illuminated component and an ambient component. The illuminated component is transmitted along an illuminated signal path and converted to a digital signal and the ambient component is transmitted along an ambient signal path and converted to a digital signal. The digitized ambient component is subtracted from the digitized illuminated component to generate a light signal with a reduced noise component.

## Claims

### Claim 1

A noise reduction circuit, comprising:
a first signal path that generates a first component of a first signal;
a second signal path that generates a second component of the first signal; and
a difference circuit having a first input coupled for receiving the first component of the first signal, a second input for receiving the second component of the first signal, and an output.

### Claim 2 (depends on 1)

The noise reduction circuit of claim 1, further comprising a receiver coupled for receiving an input signal and having an output through which the first signal is transmitted.

### Claim 3 (depends on 2)

The noise reduction circuit of claim 2, further comprising an oscillator having an output coupled to the first signal path through an inverter and coupled to the second signal path.

### Claim 4 (depends on 1)

The noise reduction circuit of claim 1, wherein the first signal path comprises:
a phase sampling circuit having an input and first and second outputs; and
a first integrating analog-to-digital circuit having an input and an output, the input of the first integrating analog-to-digital circuit coupled to the first output of the phase sampling circuit.

### Claim 5 (depends on 4)

The noise reduction circuit of claim 4, wherein the phase sampling circuit comprises:
a filtering current mirror having an input terminal and an output terminal;
a bias circuit coupled to the output terminal;
a first current mirror having an input terminal and an output terminal, the output terminal coupled to the output terminal of the filtering current mirror;
a second current mirror having an input terminal and an output terminal, the input terminal coupled to the output terminal of the filtering current mirror; and
an output stage having first and second output terminals, the output stage coupled to the output terminal of the second current mirror.

### Claim 6 (depends on 5)

The noise reduction circuit of claim 5, wherein the filtering current mirror includes a high pass filter.

### Claim 7 (depends on 1)

The noise reduction circuit of claim 1, wherein the second signal path comprises a second integrating analog-to-digital circuit having an input and an output, the input of the second integrating analog-to-digital circuit coupled to the second output of the phase sampling circuit.

### Claim 8 (depends on 1)

The noise reduction circuit of claim 1, further comprising:
a light emitting diode driver circuit coupled to the output of the oscillator; and
control logic circuitry coupled to at least the phase sampling circuit and to the light emitting diode driver circuit.

### Claim 9

A method for reducing noise, comprising:
providing a drive signal;
determining an ambient component of a first signal in response to a first portion of drive signal;
determining an illuminated component of the first signal in response to a second portion of the drive signal; and
subtracting the ambient component from the illuminated component to form an output signal.

### Claim 10 (depends on 9)

The method of claim 9, wherein the providing drive signal includes providing a light emitting diode drive signal.

### Claim 11 (depends on 10)

The method of claim 10, wherein the providing the drive signal includes providing the drive signal in response to an oscillator signal.

### Claim 12 (depends on 9)

The method of claim 9, further including generating the drive signal in response to a light emitting diode being asserted.

### Claim 13 (depends on 12)

The method of claim 12, further including sampling the first signal in response to the drive signal being asserted.

### Claim 14 (depends on 13)

The method of claim 13, further including delaying sampling the first signal for a predetermined time.

### Claim 15 (depends on 13)

The method of claim 13, further including sampling the first signal after asserting the drive signal.

### Claim 16 (depends on 9)

The method of claim 9, further including sampling the first signal in response to the drive signal being in an off state.

### Claim 17 (depends on 16)

The method of claim 16, further including sampling the first drive signal after the drive signal is de-asserted.

### Claim 18 (depends on 17)

The method of claim 17, further including delaying sampling the first signal for a predetermined time after the drive signal is de-asserted.

### Claim 19 (depends on 9)

The method of claim 9, wherein determining the ambient component of a first signal in response to a first portion of drive signal includes:
sampling the first signal;
integrating the sampled first signal to generate a first integrated signal; and
converting the first integrated signal to a first digital signal.

### Claim 20 (depends on 9)

The method of claim 9, wherein determining the illumination component of a first signal in response to a first portion of drive signal includes:
sampling the first signal;
integrating the sampled first signal to generate a second integrated signal; and
converting the second integrated signal to a second digital signal.

### Claim 21

A method for reducing noise, comprising:
sampling a first signal in response to a clock signal to generate a first sampled signal;
sampling the first signal in response to an inverted clock signal to generate a second sampled signal;
converting the first sampled signal into a first component;
converting the second sampled signal into a second component; and
subtracting the first component from the second component to generate an output signal.

### Claim 22 (depends on 21)

The method of claim 21, wherein converting the first signal into a first component includes integrating the first sampled signal to generate a first integrated sampled signal and converting the first integrated sampled signal into a digital signal.

### Claim 23 (depends on 22)

The method of claim 22, wherein converting the first signal into a second component includes integrating the second sampled signal to generate a second integrated sampled signal and converting the second integrated sampled signal into a digital signal.

### Claim 24

A phase sampling circuit, comprising:
a filtering current mirror having an input terminal and an output terminal;
a bias stage coupled to the output terminal of the filtering current mirror, wherein the bias stage increases a current flowing from the output terminal of the filtering current mirror;
a current diverter coupled to the output terminal of the filtering current mirror;
a current mirror having an input terminal coupled to the output terminal of the filtering current mirror and an output terminal; and
an output stage having an input terminal and first and second output terminals, the input terminal coupled to the output terminal of the current mirror.