# US 2013/0154720 A1 · Constant vgs switch > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0154720 A1 - Document ID: US20130154720A1 - Status: Published application - Kind: A1 - Application number: 13/331,332 - Filed: 2011-12-20 - Published: 2013-06-20 - Earliest claimed: 2011-12-20 - Assignees: Fairchild Semiconductor Corporation - Inventors: Kenneth P. Snowdon - Web page: https://patentgrep.com/patent/US20130154720A1 ## CPC - H03K 17/145: {in field-effect transistor switches} - H03K 17/6874: {in a symmetrical configuration} - H03K 2217/0018: Special modifications or use of the back gate voltage of a FET - H03K 2217/0054: Gating switches, e.g. pass gates - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract This document discusses, among other things, a signal switch circuit including a first field effect transistor (FET) configured to couple a first node to a second node in an on-state and a charge pump circuit configured to provide a first supply voltage to control the FET, wherein a reference voltage of the charge pump circuit is coupled to a well of the FET to maintain a constant gate to source voltage of the FET during the on-state. ## Claims ### Claim 1 A switch circuit defining an on-state and an off-state, the switch circuit, when in an on-state, couples a first node to a second node and, when in the off-state, isolates the first node from the second node, the switch circuit comprising: a first field effect transistor (FET) configured to couple the first node to the second node in the on-state; a power supply configured to provide a first supply voltage to control the FET; and wherein a reference voltage of the power supply is coupled to a well of the FET to maintain a constant gate to source voltage of the FET during the on-state. ### Claim 2 (depends on 1) The switch circuit of claim 1, including: a second FET coupled to the first node; a third FET coupled to the second node; and wherein the second and third FETs are configured to couple the reference voltage of the power supply to the first and second nodes during the on-state. ### Claim 3 (depends on 2) The switch circuit of claim 2, wherein an integrated circuit includes the first second and third FETs and the power supply. ### Claim 4 (depends on 2) The switch circuit of claim 2, wherein the power supply includes first and second charge pumps. ### Claim 5 (depends on 4) The switch circuit of claim 4, wherein the first and second charge pumps are configured to receive a regulated supply voltage. ### Claim 6 (depends on 5) The switch circuit of claim 5, including a clock buffer configured to receive a first charge pump clock signal and to provide a second charge pump clock signal using the regulated supply voltage. ### Claim 7 (depends on 4) The switch circuit of claim 4, wherein the difference between the first supply voltage and the reference voltage of the charge pump is configured to be greater than a voltage swing of a signal applied to the first node. ### Claim 8 (depends on 1) The switch circuit of claim 1, including a translation circuit configured to reference a control signal of the FET to the lower of a second supply voltage or a signal applied to the first node. ### Claim 9 (depends on 8) The switch circuit of claim 8, including an under voltage circuit configured to provide the signal applied to the first node to the translation circuit when a voltage of the signal applied to the first node is below the second supply voltage. ### Claim 10 (depends on 9) The switch circuit of claim 9, including a fourth FET configured to couple the reference voltage of the power supply to the signal applied to the first node when the signal applied to the first node is at a voltage level lower than the second supply voltage. ### Claim 11 (depends on 9) The switch circuit of claim 9, including a switch control buffer configured to receive the control signal from the translation circuit, to provide a first control signal to the FET, and to provide a second control signal to the fourth FET. ### Claim 12 (depends on 1) The switch circuit of claim 1, wherein the first FET is configured to couple to at least one of a universal serial bus (USB) data line, a mobile high-definition link (MHL) data line, or an audio signal. ### Claim 13 A method for operating a switch circuit that includes an on-state and an off-state, the switch circuit, when in an on-state, couples a first node to a second node and, when in the off-state, isolates the first node from the second node, the method comprising: providing a first supply voltage using a charge pump; controlling a field effect transistor (FET) using the first supply voltage, the FET coupled between the first node and the second node; and referencing a well of the FET to a reference voltage of the charge pump to maintain a constant gate to source voltage of the FET during the on-state. ### Claim 14 (depends on 13) The method of claim 13, including coupling the reference voltage of the charge pump to the first node during the on-state using a second FET. ### Claim 15 (depends on 14) The method of claim 14, including coupling the reference voltage of the charge pump to the second node during the on-state using a third FET. ### Claim 16 (depends on 13) The method of claim 13, wherein the providing a first supply voltage includes receiving a regulated supply voltage at the charge pump. ### Claim 17 (depends on 13) The method of claim 13, including referencing a control signal of the FET to the lower of a second supply voltage or a voltage of a signal applied to the first node using a translation circuit. ### Claim 18 (depends on 17) The method of claim 17, wherein the referencing a control signal includes receiving the signal applied to the first node at the translation circuit when a voltage of the signal applied to the first node is below the second supply voltage. ### Claim 19 (depends on 17) The method of claim 17, including coupling the signal applied to the first node with the reference voltage using a fourth FET when the signal applied to the first node is at a voltage level lower than the second supply voltage. ### Claim 20 (depends on 19) The method of claim 19 including: providing the control signal of the FET from a switch control buffer; and providing a control signal of the fourth FET from the switch control buffer.