# US 2013/0154718 A1 · Fully Capacitive Coupled Input Choppers

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- Number: US 2013/0154718 A1
- Document ID: US20130154718A1
- Status: Published application
- Kind: A1
- Application number: 13/325,847
- Filed: 2011-12-14
- Published: 2013-06-20
- Earliest claimed: 2011-12-14
- Assignees: Maxim Integrated Products, Inc.
- Inventors: Johan Hendrik Huijsing; Qinwen Fan; Kofi Afolabi Anthony Makinwa
- Web page: https://patentgrep.com/patent/US20130154718A1

## CPC

- H03K 17/08104: {in field-effect transistor switches (H03K17/0812, H03K17/0814 take precedence)}
- H03F 1/523: {for amplifiers using field-effect devices (H03F1/526 takes precedence)}
- H03F 3/393: with field-effect devices
- H03F 3/45179: {using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence)}
- H03M 3/34: {by chopping}
- H03F 2200/261: Amplifier which being suitable for instrumentation applications
- H03M 3/43: {the quantiser being a single bit one}
- H03M 3/452: {with weighted feedforward summation, i.e. with feedforward paths from more than one filter stage to the quantiser input}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H03F: AMPLIFIERS
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A method of differential signal transfer from a differential input Vinp and Vinn having a common mode input voltage that can be higher than the power supply voltage by providing an input chopper having Vinp and Vinn as a differential input, providing an output chopper, capacitively coupling a differential output Voutp and Voutn of the input chopper to a differential input of the output chopper, capacitively coupling a clock to the input chopper and coupling the clock to the output chopper, the clock having a first phase and a second phase opposite from the first phase, the first phase being coupled to the gates of the first and second transistors and the second phase being coupled to the gates of the third and fourth transistors, and providing protection of the gates of the first through fourth transistors from excessive voltages. Various embodiments are disclosed.

## Claims

### Claim 1

A method of differential signal transfer from a differential input Vinp and Vinn having a common mode input voltage that can be higher than the power supply voltage, comprising:
providing an input chopper having first through fourth chopper transistors, each having a source, a drain and a gate, the input chopper having Vinp and Vinn as a differential input;
providing an output chopper;
capacitively coupling a differential output Voutp and Voutn of the input chopper to a differential input of the output chopper;
capacitively coupling a clock to the input chopper and coupling the clock to the output chopper, the clock having a first phase and a second phase opposite from the first phase, the first phase being capacitively coupled to the gates of the first and second transistors and the second phase being capacitively coupled to the gates of the third and fourth transistors; and,
providing protection of the gates of the first through fourth transistors from excessive voltages.

### Claim 2 (depends on 1)

The method of claim 1 wherein the first through fourth transistors are MOS transistors, and wherein the sources of the first and third transistors are coupled to the Vinp input, the sources of the second and fourth transistors are coupled to the Vinn input, the drains of the first and fourth transistors are coupled to input chopper output Voutp and the drains of the second and third transistors being coupled to the input chopper output Voutn.

### Claim 3 (depends on 2)

The method of claim 2 wherein providing protection of the gates of the first through fourth transistors from excessive voltages comprises coupling diodes between the respective gates and sources of the first through fourth transistors, some in a series connection with a polarity to limit the gate source voltage tending to turn on the respective transistor and at least one diode of the opposite polarity between the respective sources and drains.

### Claim 4 (depends on 2)

The method of claim 2 further comprised of providing protection of the first through fourth transistors from excessive drain source voltages.

### Claim 5 (depends on 4)

The method of claim 4 wherein providing protection of the first through fourth transistors from excessive drain source voltages comprises coupling a diode or a series connection of multiple diodes between the drain and source of each of the first and second transistors, the diodes having a polarity opposite the polarity of the respective body diode.

### Claim 6 (depends on 2)

The method of claim 2 further comprised of providing protection for the first through fourth transistors against a negative common mode input voltage step.

### Claim 7 (depends on 6)

The method of claim 6 wherein providing protection of the gates of the first through fourth transistors from excessive voltages comprises, when a negative common mode voltage surge occurs on the inputs Vinp and Vinn, coupling the gates of the first and third transistors to the input Vinp, and coupling the gates of the second and fourth transistors to the input Vinn.

### Claim 8 (depends on 7)

The method of claim 7 wherein the coupling the gates of the first and third transistors to the input Vinp comprises capacitively coupling a diode connected fifth transistor between ground and the input Vinp, and coupling first replica transistors to the gates of the first and third transistors, the first replica transistors replicating a conduction state of the diode connected fifth transistor to turn on the first replica transistors when a negative surge on the input Vinp reverses the voltage across the diode connected fifth transistor, and wherein the coupling the gates of the second and fourth transistors to the input Vinn comprises capacitively coupling a diode connected sixth transistor between ground and the input Vinn, and coupling second replica transistors to the gates of the second and fourth transistors, the second replica transistors replicating a conduction state of the diode connected sixth transistor to turn on when a negative surge on the input Vinn reverses the voltage across the diode connected sixth transistor.

### Claim 9 (depends on 8)

The method of claim 8 further comprising providing protection of the first through fourth transistors from excessive drain source voltages by coupling a diode or a series connection of multiple diodes between the drain and source of each of the first and second transistors, the diodes having a polarity opposite the polarity of the respective body diodes of the first and second transistors.

### Claim 10 (depends on 6)

The method of claim 6 wherein providing protection of the gates of the first through fourth transistors from excessive voltages comprises, when a negative common mode voltage surge occurs on the inputs Vinp and Vinn, coupling the gates of the first through fourth transistors to the input Vinp or the input Vinn, which ever is a lower voltage.

### Claim 11 (depends on 10)

The method of claim 10 wherein the coupling the gates of the first through fourth transistors to the input Vinp or the input Vinn, which ever is a lower voltage comprises capacitively coupling a diode connected fifth transistor between ground and the input Vinp or Vinn, which ever has a lower voltage, and coupling a first one replica transistor to the gates of the first and second transistors and coupling a second replica transistor to the gates of the third and fourth transistors, the replica transistors replicating a conduction state of the diode connected fifth transistor to turn on the replica transistors when a negative surge on the input Vinp or Vinn, which ever is a lower voltage, reverses the voltage across the diode connected fifth transistor.

### Claim 12 (depends on 11)

The method of claim 11 wherein which of the inputs Vinp or Vinn is a lower voltage is determined by providing a latch responsive the inputs Vinp and Vinn.

### Claim 13 (depends on 12)

The method of claim 12 further comprising providing protection of the first through fourth transistors from excessive drain source voltages by coupling a diode or a series connection of multiple diodes between the drain and source of each of the first and second transistors, the diodes having a polarity opposite the polarity of the respective body diodes of the first and second transistors.

### Claim 14 (depends on 6)

The method of claim 6 wherein providing protection of the gates of the first through fourth transistors from excessive voltages comprises, when a negative common mode voltage surge occurs on the inputs Vinp and Vinn, coupling the gates of the first through fourth transistors to one of the inputs Vinp or Vinn.

### Claim 15 (depends on 14)

The method of claim 14 wherein coupling the gates of the first and second transistors to the input Vinp or Vinn comprises capacitively coupling a diode connected fifth transistor between ground and the respective input Vinp or Vinn, and coupling a first replica transistor to the gates of the first and second transistors and coupling a second replica transistor to the gates of the third and fourth transistors, the replica transistors replicating a conduction state of the diode connected fifth transistor to turn on the replica transistors when a negative surge on the input coupled to the diode connected fifth transistor reverses the voltage across the diode connected fifth transistor.

### Claim 16 (depends on 15)

The method of claim 15 further comprising providing protection of the first through fourth transistors from excessive drain source voltages by coupling a diode or a series connection of multiple diodes between the drain and source of each of the first and second transistors, the diodes having a polarity opposite the polarity of the respective body diodes of the first and second transistors.

### Claim 17 (depends on 15)

The method of claim 15 further comprising:
accurately defining the start voltages of the gates of the first through fourth transistors for a next clock inversion by providing a latch having a first latch connection to the gates of the first and second transistors, and a second latch connection to the gates of the third and fourth transistors, respectively.

### Claim 18 (depends on 2)

The method of claim 2 further comprising:
accurately defining the start voltages of the gates of transistors MN1 through MN4 for a next clock inversion by providing a first latch having a first latch connection coupled to the gates of the first and second transistors, and a second latch connection coupled to the gates of the third and fourth transistors, respectively, the latch having a common connection coupled to one to one of the inputs Vinp and Vinn.

### Claim 19 (depends on 18)

The method of claim 18 further comprising:
accurately defining the start voltages of the gates of the first through eighth transistors for a next clock inversion by providing a first latch between the gates of the first and second transistors, a second latch between the gates of the third and fourth transistors, a third latch between the fifth and sixth transistors and a fourth latch between the seventh and eighth transistors, respectively, the first latch having a common connection coupled to the input Vinp, the second latch having a common connection coupled to the input Vinn, the third latch having a common connection coupled to the input chopper output Voutn, and the fourth latch having a common connection coupled to the input chopper output Voutp.