# US 2013/0154716 A1 · Circuit Topology for a Phase Connection of an Inverter

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- Number: US 2013/0154716 A1
- Document ID: US20130154716A1
- Status: Published application
- Kind: A1
- Application number: 13/686,089
- Filed: 2012-11-27
- Published: 2013-06-20
- Earliest claimed: 2010-06-12
- Assignees: Kostal Industrie Elektrik GmbH
- Inventors: Martin Degener; Michael Kretschmann
- Web page: https://patentgrep.com/patent/US20130154716A1

## CPC

- H03K 3/012: Modifications of generator to improve response time or to decrease power consumption
- H02M 7/487: Neutral point clamped inverters
- H02M 7/5388: with asymmetrical configuration of switches
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)

## Abstract

A circuit for a phase connection of an inverter includes upper and lower bridge halves and respectively associated upper and lower bridge segments. Each bridge half has an outer switch and an inner switch connected in series. Each bridge segment has a diode and the inner switch of the associated bridge half connected in series. An output of the circuit is respectively connected to upper and lower potentials through the outer switches and is further connected to a center potential applied between the upper and lower potentials through each of the upper and lower bridge segments. Each bridge half further has a parallel power switch. The parallel switch of each bridge half is connected in parallel to the series-connected outer and inner switches of the bridge half. The output of the circuit is further respectively connected to the upper and lower potentials through the parallel switches.

## Claims

### Claim 1

A circuit topology for a phase connection of an inverter, the circuit topology comprising:
a circuit bridge having upper and lower bridge halves and upper and lower bridge segments respectively associated with the upper and lower bridge halves, wherein each bridge half has an outer switch and an inner switch connected in series, wherein each bridge segment has a diode and the inner switch of the associated bridge half connected in series;
the circuit bridge having an output respectively connected to upper and lower potentials through the outer switches of the upper and lower bridge halves, the output of the circuit bridge further connected to a center potential applied between the upper and lower potentials through each of the upper and lower bridge segments;
each of the upper and lower bridge halves further has a parallel power switch, wherein the parallel switch of each bridge half is connected in parallel to the series-connected outer and inner switches of the bridge half;
the output of the circuit bridge being further respectively connected to the upper and lower potentials through the parallel switches of the upper and lower bridge halves.

### Claim 2 (depends on 1)

The circuit topology of claim 1 wherein:
the outer and inner switches of the upper and lower bridge halves are configured to produce relatively small switching losses and comparable relatively large conduction losses.

### Claim 3 (depends on 2)

The circuit topology of claim 2 wherein:
the parallel switches of the upper and lower bridge halves are configured to produce relatively small conduction losses and comparable relatively large switching losses.

### Claim 4 (depends on 1)

The circuit topology of claim 1 wherein:
the parallel switches of the upper and lower bridge halves are configured to produce relatively small conduction losses and comparable relatively large switching losses.

### Claim 5 (depends on 1)

The circuit topology of claim 1 wherein:
the outer and inner switches of the upper and lower bridge halves are MOSFETs.

### Claim 6 (depends on 5)

The circuit topology of claim 5 wherein:
the parallel switches of the upper and lower bridge halves are IGBTs.

### Claim 7 (depends on 1)

The circuit topology of claim 1 wherein:
the parallel switches of the upper and lower bridge halves are IGBTs.

### Claim 8

A method for producing a phased output voltage of an inverter by a circuit bridge having upper and lower bridge halves and upper and lower bridge segments respectively associated with the upper and lower bridge halves, each bridge half having an outer switch and an inner switch connected in series, each bridge segment having a diode and the inner switch of the associated bridge half connected in series, an output of the circuit bridge respectively connected to upper and lower potentials through the outer switches and further connected to a center potential applied between the upper and lower potentials through each of the bridge segments, each of the bridge halves further having a parallel power switch, the parallel switch of each bridge half being connected in parallel to the series-connected outer and inner switches of the bridge half, and the output of the circuit bridge being further respectively connected to the upper and lower potentials through the parallel switches, the method comprising:
initiating a sequence of a switching pulse over a time period at whose beginning and end the inner switch of the upper bridge half is closed and all of the other switches are opened with the bridge output being connected to the center potential through upper bridge segment via the diode of the upper bridge segment and the inner switch of the upper bridge half;
closing the outer switch of the upper bridge half;
closing the parallel switches after a delay time that is a fraction of the time period of the switching pulse;
opening the parallel switches shortly before the end of the switching pulse; and
opening the outer switch of the upper bridge half after a delay time that is a fraction of the time period of the switching pulse.

### Claim 9 (depends on 8)

The method of claim 8 wherein:
the outer and inner switches are configured to produce relatively small switching losses and comparable relatively large conduction losses.

### Claim 10 (depends on 9)

The method of claim 9 wherein:
the parallel switches are configured to produce relatively small conduction losses and comparable relatively large switching losses.

### Claim 11 (depends on 8)

The method of claim 8 wherein:
the parallel switches are configured to produce relatively small conduction losses and comparable relatively large switching losses.

### Claim 12 (depends on 8)

The method of claim 8 wherein:
the outer and inner switches are MOSFETs.

### Claim 13 (depends on 12)

The method of claim 12 wherein:
the parallel switches are IGBTs.

### Claim 14 (depends on 8)

The method of claim 8 wherein:
the parallel switches are IGBTs