# US 2013/0154714 A1 · Current-mode sample and hold for dead time control of switched mode regulators

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- Number: US 2013/0154714 A1
- Document ID: US20130154714A1
- Status: Published application
- Kind: A1
- Application number: 13/719,577
- Filed: 2012-12-19
- Published: 2013-06-20
- Earliest claimed: 2011-12-20
- Assignees: Conexant Systems, Inc.
- Inventors: Brian W. Friend; Kyehyung Lee
- Web page: https://patentgrep.com/patent/US20130154714A1

## CPC

- H03K 17/56: by the use, as active elements, of semiconductor devices (using diodes H03K17/74)
- H02M 1/38: Means for preventing simultaneous conduction of switches
- H03K 17/167: {using parallel switching arrangements}
- H03K 17/6872: {using complementary field-effect transistors}
- H02M 1/0009: {Devices or circuits for detecting current in a converter}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)

## Abstract

A system for current mode sample and hold, comprising a first PMOS transistor configured to generate a current to be sampled. A diode-connected NMOS transistor coupled to the first PMOS transistor and configured to receive the current. A switch coupled to the diode-connected NMOS transistor and configured to sample a gate-source voltage of the diode-connected NMOS transistor. A capacitor coupled to the switch and configured to stored the gate-source voltage of the diode-connected NMOS transistor. A second NMOS transistor coupled to the capacitor and configured to generate a current equal to the sampled current value.

## Claims

### Claim 1

A system for current mode sample and hold, comprising:
a first PMOS transistor configured to generate a current to be sampled;
a diode-connected NMOS transistor coupled to the first PMOS transistor and configured to receive the current;
a switch coupled to the diode-connected NMOS transistor and configured to sample a gate-source voltage of the diode-connected NMOS transistor;
a capacitor coupled to the switch and configured to stored the gate-source voltage of the diode-connected NMOS transistor;
a second NMOS transistor coupled to the capacitor and configured to generate a current equal to the sampled current value.

### Claim 2 (depends on 1)

The system of claim 1 further comprising a diode-connected PMOS transistor and a second PMOS transistor configured to generate the sampled current and provide the sampled current to analog current controlled delay.

### Claim 3 (depends on 1)

The system or claim 1 wherein the first PMOS transistor is coupled to a power module, and the current to be sampled is derived from a current of the power module.

### Claim 4 (depends on 3)

The system of claim 3 further comprising a dead time control configured to receive the sampled current value and to generate dead time control data for generation of control pulses for PMOS transistors and NMOS transistors of a power module.

### Claim 5 (depends on 4)

The system of claim 4 further comprising a width control coupled to the power module and the dead time control, the width control configured to receive the dead time control data to control a pulse width of the control pulses for the PMOS transistors and the NMOS transistors of the power module.

### Claim 6 (depends on 3)

The system of claim 3 further comprising:
a load coupled to the power module; and
an adaptive loop compensator coupled to the load and configured to cancel out a load current dependent load pole.

### Claim 7

A method for current mode sample and hold, comprising:
receiving a current to be sampled at an input device;
actuating a sample switch to sample a current value; and
storing a parameter using a storage capacitance that is connected in parallel with the input device.

### Claim 8 (depends on 7)

The method of claim 7 wherein the input device comprises a diode-connected NFET transistor.

### Claim 9 (depends on 7)

The method of claim 7 wherein the input device comprises a diode-connected PFET transistor.

### Claim 10 (depends on 7)

The method of claim 7 wherein actuating the sample switch comprises actuating the sample switch based on an input voltage from a power MOS module.

### Claim 11 (depends on 7)

The method of claim 7 wherein actuating the sample switch comprises actuating the sample switch based on an input current value from a power MOS module.

### Claim 12 (depends on 7)

The method of claim 7 wherein actuating the sample switch comprises actuating the sample switch based on timing data.

### Claim 13

The hod of claim wherein actuating the sample switch to sample the current value comprises actuating the sample switch to sample a load current value.

### Claim 14 (depends on 7)

The method of claim 7 wherein storing the parameter using the storage capacitance that is connected in parallel with the input device comprises storing a gate to source voltage of a diode-connected NFET.

### Claim 15

A system for current mode sample and hold control of a power module, comprising:
means for current mode sample and hold coupled to the power module and configured to receive a current to be sampled from the power module;
means for control current signal conditioning and scaling coupled to the means for current mode sample and hold and configured to condition and scale a sampled current value; and
means for providing a controllable delay for P off to N on dead time control coupled to the means for control current signal conditioning and scaling and to the power module and configured to receive the conditioned and scaled sampled current value and to generate controllable delay data for turning one or more PMOS transistor of the power module off and one or more NMOS transistor of the power module on.

### Claim 16 (depends on 15)

The system of claim 15 wherein the means for current mode sample and hold comprises a diode-connected PFET.

### Claim 17 (depends on 15)

The system of claim 15 wherein the means for control current signal conditioning and scaling comprises a PFET coupled to a first NFET current mirror with a first bias current source IB1 and coupled to a pair of PFETs connected as a current mirror and driven by second bias current source IB, an also coupled to a second NFET current mirror.

### Claim 18 (depends on 15)

The system of claim 15 wherein the means for providing the controllable delay for P off to N on dead time control comprises a plurality of inverter stages coupled to NFET/PFET pairs.

### Claim 19 (depends on 15)

The system of claim 15 further comprising means for non-overlapping power switch control.

### Claim 20 (depends on 15)

The system of claim 15 further comprising means for providing a fixed delay for non-critical N off to P on dead time control.