# US 2013/0154712 A1 · Multiplexer with Level Shifter

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- Number: US 2013/0154712 A1
- Document ID: US20130154712A1
- Status: Published application
- Kind: A1
- Application number: 13/326,932
- Filed: 2011-12-15
- Published: 2013-06-20
- Earliest claimed: 2011-12-15
- Assignees: Apple Inc.
- Inventors: Greg M. Hess; Naveen Javarappa; James E. Burnette, II
- Web page: https://patentgrep.com/patent/US20130154712A1

## CPC

- H03K 3/35613: {the input circuit having a differential configuration}
- H03K 19/018521: {of complementary type, e.g. CMOS}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A level shifting multiplexer is disclosed. In one embodiment, a multiplexer is coupled to receive a first input signal from circuitry in a first power domain and a second input signal from circuitry in a second power domain. The multiplexer is configured to output a selected one of the first and second input signals to circuitry in the second power domain. The multiplexer also includes a level shifter circuit. When the first input signal is selected, the level shifter circuit may be enabled. When enabled, the level shifter circuit may level shift the first signal such that its voltage swing corresponds to that of the second voltage domain. The multiplexer may also include isolation circuitry configured to inhibit the level shifter.

## Claims

### Claim 1

An apparatus comprising:
a level shifter circuit coupled between a first input node in a first voltage domain and an output node in a second voltage domain, wherein the level shifter circuit is configured to receive a first input signal on the first input node, wherein the level shifter is configured to drive an output signal corresponding to the first input signal on the output node responsive to a first state of a select signal;
a first pull-up transistor configured to pull the output node up to an operating voltage of the second voltage domain responsive to a second state of the select signal and a first state of a second input signal; and
a pull-down transistor configured to pull the output node down to a ground voltage responsive to a second state of the select signal and a second state of the second input signal.

### Claim 2 (depends on 1)

The apparatus as recited in claim 1, further comprising isolation circuitry coupled to receive an isolation signal, wherein the isolation circuitry is configured to inhibit the level shifter circuit from driving the output node when the isolation signal is asserted.

### Claim 3 (depends on 2)

The apparatus as recited in claim 2, wherein the isolation circuitry is further coupled to receive the select signal, wherein the isolation circuitry is configured to inhibit the level shifter circuit from driving the output node when the select signal is in the second state.

### Claim 4 (depends on 2)

The apparatus as recited in claim 2, further comprising a second pull-up transistor configured to pull the output node up to an operating voltage of the second voltage domain responsive to assertion of the isolation signal and the select signal being in the first state.

### Claim 5 (depends on 2)

The apparatus as recited in claim 2, wherein the first input signal is generated in the first voltage domain, and wherein the second input signal, the isolation signal, and the select signal are each generated in the second voltage domain.

### Claim 6

A method comprising:
a multiplexer selecting a first signal received from a first functional unit operating in a first voltage domain;
level shifting and outputting the first signal to a second functional unit operating in a second voltage domain;
selecting, using the multiplexer, a second signal received from a third functional unit operating in the second voltage domain; and
outputting the second signal to the second functional unit.

### Claim 7 (depends on 6)

The method as recited in claim 6, further comprising:
receiving a selection signal from a circuit operating in the second voltage domain;
selecting, using the multiplexer, the first signal responsive to the selection signal being in a first state; and
selecting, using the multiplexer, the second signal responsive to the selection signal being in a second state.

### Claim 8 (depends on 7)

The method as recited in claim 7, further comprising:
inhibiting level shifting of the first signal responsive to receiving an isolation signal; and
inhibiting level shifting of the first signal responsive to receiving the selection signal in the second state.

### Claim 9 (depends on 8)

The method as recited in claim 8, further comprising driving an output node of the multiplexer to a known state responsive to receiving the isolation signal and receiving the selection signal in the first state.

### Claim 10 (depends on 7)

The method as recited in claim 7, further comprising:
a pull-down transistor pulling an output node of the multiplexer down toward a ground voltage responsive to the second input signal being in the first state and the selection signal being in the second state; and
a pull-up transistor pulling the output of the multiplexer up toward an operating voltage of the second voltage domain responsive to the second signal being in the second state and the selection signal being in the second state.

### Claim 11

A circuit comprising:
a level shifter configured to receive a first input signal from a first voltage domain to provide an output signal in a second voltage domain;
a first transistor coupled to an output of the level shifter and configured to pull the output node up in response to a second input signal in the second voltage domain, wherein the output of the level shifter is in the second voltage domain; and
a second transistor coupled to the output and configured to pull the node down in response to a second input signal;
wherein the first transistor, the second transistor, and the level shifter are further controlled response to a select signal that selects between the first input signal and the second input signal.

### Claim 12 (depends on 11)

The circuit as recited in claim 11, wherein the circuit further includes an isolation circuit coupled to the level shifter, wherein the isolation circuit is configured to inhibit the level shifter circuit from providing the output signal in the second voltage domain responsive to receiving an isolation signal.

### Claim 13 (depends on 12)

The circuit as recited in claim 12, wherein the isolation signal is further configured to inhibit the level shifter circuit from providing the output signal in the second voltage domain responsive to the select signal being in a logic high state.

### Claim 14 (depends on 11)

The circuit as recited in claim 11, wherein the first transistor is configured to pull the output node up responsive to the select signal being in a logic high state and the second input signal being in a logic high state.

### Claim 15 (depends on 11)

The circuit as recited in claim 11, wherein the second transistor is configured to pull the output node down responsive to the select signal being in a logic high state and the second input signal being in a logic low state.

### Claim 16

An integrated circuit comprising:
a first functional unit configured to operate at a first voltage;
a second functional unit configured to operate at a second voltage; and
a multiplexer coupled to receive a first signal from the first functional unit and a second signal from the second functional unit, wherein the multiplexer is configured to:
select the first input signal responsive to receiving a selection signal in a first state;
select the second input signal responsive to receiving the selection signal in a second state; and
output the selected one of the first or second signals to a third functional unit operating at the second voltage, wherein the multiplexer is configured to level shift the first input signal responsive receiving the selection signal in the first state.

### Claim 17 (depends on 16)

The integrated circuit as recited in claim 16, wherein the multiplexer includes a first pull-up transistor configured to pull an output node of the multiplexer up toward the second voltage responsive to receiving the select signal in the second state and the second input signal in the second state.

### Claim 18 (depends on 17)

The integrated circuit as recited in claim 17, wherein the multiplexer includes a pull-down transistor configured to pull the output node of the multiplexer down toward a ground voltage responsive to receiving the select signal in the first state and the select signal in the second state,

### Claim 19 (depends on 17)

The integrated circuit as recited in claim 17, wherein the multiplexer includes:
a level shifter circuit configured to level shift the first input signal when the selection signal is in the first state; and
isolation circuitry configured to inhibit the level shifter from level shifting the first input signal responsive to assertion of an isolation signal or receiving the selection signal in the second state.

### Claim 20 (depends on 19)

The integrated circuit as recited in claim 19, further comprising a second pull-up transistor configured to pull the output node up toward the second voltage responsive to the isolation signal being asserted and the select signal being in the first state.

### Claim 21

A system comprising:
a first circuit configured to generate a first signal in a first voltage domain;
a second circuit configured to generate a second signal in a second voltage domain;
a third circuit coupled to receive the first signal and the second signal and configured to output a selected one of the first and second signals to a fourth circuit in the second voltage domain, wherein the third circuit is configured to level shift the first signal responsive to the third circuit selecting the first signal.

### Claim 22 (depends on 21)

The system as recited in claim 21, wherein the third circuit is coupled to receive a selection signal, wherein the third circuit is configured is configured to select the first input signal responsive to receiving the selection signal as a logic low, and further configured to select the second input signal responsive to receiving the selection signal as a logic high.

### Claim 23 (depends on 22)

The system as recited in claim 22, wherein the third circuit includes an output node, wherein the third circuit is configured to drive the output node to a logical state equivalent to that of the second signal responsive to receiving the selection signal as a logic high.

### Claim 24 (depends on 22)

The system as recited in claim 22, wherein the third circuit includes a level shifter configured to level shift the first signal, wherein the third is configured to inhibit the level shifter responsive to receiving an asserted isolation signal or receiving the selection signal as a logic high.

### Claim 25 (depends on 24)

The system as recited in claim 24, wherein the third circuit is configured to drive the output node to a logical state equivalent to that of the first input signal when the selection signal is a logic low and the isolation signal is de-asserted.