# US 2013/0154710 A1 · Adaptive cascode circuit using mos transistors

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- Number: US 2013/0154710 A1
- Document ID: US20130154710A1
- Status: Published application
- Kind: A1
- Application number: 13/711,447
- Filed: 2012-12-11
- Published: 2013-06-20
- Earliest claimed: 2011-12-15
- Assignees: Silergy Semiconductor Technology (Hangzhou) LTD
- Inventors: Michael Grimm; Jun Chen
- Web page: https://patentgrep.com/patent/US20130154710A1

## CPC

- H03K 17/102: {in field-effect transistor switches}
- G05F 3/02: Regulating voltage or current
- H02M 3/33507: {with automatic control of the output voltage or current, e.g. flyback converters (H02M3/33561, H02M3/33569 take precedence)}
- H03K 5/084: {modified by switching, e.g. by a periodic signal or by a signal in synchronism with the transitions of the output signal}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)

## Abstract

The present invention relates to a cascode circuit using MOS transistors. In one embodiment, an adaptive cascode circuit can include: (i) a main MOS transistor; (ii) n adaptive MOS transistors coupled in series to the drain of the main MOS transistor, where n can be an integer greater than one; (iii) a shutdown clamping circuit connected to the gates of the n adaptive MOS transistors, where the shutdown clamping circuit may have (n+1) shutdown clamping voltages no larger than rated gate-drain voltages of the main MOS transistor and n adaptive MOS transistors; and (iv) n conduction clamping circuits coupled correspondingly to the gates of the adaptive MOS transistors, where the n conduction clamping circuits may have n conduction clamping voltages no larger than the conduction threshold voltages of the adaptive MOS transistors.

## Claims

### Claim 1

An adaptive cascode circuit, comprising:
a) a main MOS transistor, wherein a source of said main MOS transistor is configured as a first terminal of said adaptive cascode circuit, and wherein a gate of said main MOS transistor is configured as a control terminal of said adaptive cascode circuit;
b) n adaptive MOS transistors coupled in series to a drain of said main MOS transistor, wherein a drain of a first adaptive MOS transistor is configured as a second terminal of said adaptive cascode circuit, and wherein n is an integer greater than one;
c) a shutdown clamping circuit coupled to gates of said n adaptive MOS transistors, wherein said shutdown clamping circuit comprises (n+1) shutdown clamping voltages that are less than corresponding rated drain-gate voltages of said main MOS transistor and said n adaptive MOS transistors; and
d) n conduction clamping circuits coupled to gates of corresponding said n adaptive MOS transistors, wherein said n conduction clamping circuits comprise n conduction clamping voltages greater than corresponding conduction threshold voltages of said adaptive MOS transistors;
e) wherein when said main MOS transistor and said n adaptive MOS transistors are shutdown, and drain-gate voltages of said main MOS transistor and said n adaptive MOS transistors are larger than said shutdown clamping voltages, said shutdown clamping circuit is configured to clamp drain-gate voltages of said main MOS transistor and said adaptive MOS transistors to corresponding said shutdown clamping voltages, wherein said drain-gate voltages of said main MOS transistor and said adaptive MOS transistors are configured to be no larger than said rated drain-gate voltages of said main MOS transistor and said n adaptive MOS transistors;
f) wherein when said n adaptive MOS transistors and said main MOS transistor are conducting, said conduction clamping circuit is configured to clamp said gate voltages of said n adaptive MOS transistors to corresponding said n conduction clamping voltages.

### Claim 2 (depends on 1)

The adaptive cascode circuit of claim 1, further comprising:
a) n gate-source clamping circuits coupled between gates and sources of corresponding said n adaptive MOS transistors, wherein said n gate-source clamping circuits comprise n gate-source clamping voltages no larger than rated gate-source voltages of said n adaptive MOS transistors; and
b) wherein when said n adaptive MOS transistors and said main MOS transistor are conducting, said gate-source clamping circuits are configured to clamp gate-source voltages of said n adaptive MOS transistors to corresponding said n gate-source clamping voltages.

### Claim 3 (depends on 1)

The adaptive cascode circuit of claim 1, wherein:
a) said n adaptive MOS transistors and said main MOS transistor comprise N-type MOS transistors, a first terminal of said shutdown clamping circuit is coupled to a second terminal of said adaptive cascode circuit, and a second terminal of said shutdown clamping circuit is coupled to ground; and
b) each of said conduction clamping circuits comprises a first diode, wherein a cathode of said first diode is coupled to a gate of a corresponding said adaptive transistor, and an anode of said first diode is coupled to a voltage source.

### Claim 4 (depends on 2)

The adaptive cascode circuit of claim 2, wherein:
a) said adaptive MOS transistors and main MOS transistor comprise N-type MOS transistors, and each of said n gate-source clamping circuits comprises a first zener diode; and
b) an anode of said first zener diode is coupled to a source of a corresponding said adaptive MOS transistor, and a cathode of said first zener diode is coupled to a gate of a corresponding said adaptive MOS transistor.

### Claim 5 (depends on 1)

The adaptive cascode circuit of claim 1, wherein:
a) said adaptive MOS transistors and said main MOS transistor comprise P-type MOS transistors, a first terminal of said shutdown clamping circuit is coupled to a highest voltage, and a second terminal of said shutdown clamping circuit is coupled to a second terminal of said adaptive cascode circuit; and
b) each of said conduction clamping circuits comprises a second diode, wherein an anode of said second diode is coupled to a gate of a corresponding said adaptive MOS transistor, and a cathode of said second diode is coupled to a voltage source with a value of a difference voltage between said highest voltage and a rated gate-source voltage of said main MOS transistor.

### Claim 6 (depends on 2)

The adaptive cascode circuit of claim 2, wherein:
a) said adaptive MOS transistors and said main MOS transistor comprise P-type MOS transistor, each of said gate-source clamping circuits comprises a second zener diode; and
b) an anode of said second zener diode is coupled to a gate of a corresponding said adaptive MOS transistor, and a cathode of said first zener diode is coupled to a source of a corresponding said adaptive MOS transistor.

### Claim 7 (depends on 3)

The adaptive cascode circuit of claim 3, wherein:
a) said shutdown clamping circuit comprises series coupled (n+1) third zener diodes, wherein n common nodes of said (n+1) third zener diodes are respectively coupled to gates of said n adaptive MOS transistors;
b) a cathode of a first of said third zener diodes is configured as a first terminal of said shutdown clamping circuit to couple with a second terminal of said adaptive cascode circuit; and
c) an anode of said nth of said third zener diodes is configured as a second terminal of said shutdown clamping circuit to couple with ground.

### Claim 8 (depends on 7)

The adaptive cascode circuit of claim 7, further comprising a third diode, wherein an anode of said third diode is coupled to a second terminal of said cascode circuit, and wherein a cathode of said third diode is coupled to a first terminal of said shutdown clamping circuit.

### Claim 9 (depends on 5)

The adaptive cascode circuit of claim 5, wherein:
a) said shutdown clamping circuit comprises series coupled (n+1) fourth zener diodes, wherein n common nodes of said (n+1) fourth zener diodes are respectively coupled to gates of said n adaptive MOS transistors;
b) an anode of a first of said fourth zener diodes is configured as a second terminal of said shutdown clamping circuit to couple with a second terminal of said cascode circuit; and
c) a cathode of the (n+1)th of said fourth zener diodes is configured as a first terminal of said shutdown clamping circuit to couple with a highest voltage.

### Claim 10 (depends on 9)

The adaptive cascode circuit of claim 9, further comprising a fourth diode, wherein a cathode of said fourth diode is coupled to a second terminal of said adaptive cascode circuit, and an anode of said fourth diode is coupled to a second terminal of said shutdown clamping circuit.

### Claim 11 (depends on 1)

The adaptive cascode circuit of claim 1, wherein:
a) said adaptive MOS transistors and said main MOS transistor comprise N-type MOS transistors, said adaptive MOS transistors are coupled to at least one of a plurality of enhanced drivers, wherein each of said enhanced drivers comprises a push-pull circuit and a fifth diode;
b) an input terminal of said push-pull circuit is coupled to a corresponding said conduction clamping circuit, and an output terminal of said push-pull circuit is coupled to a gate of a corresponding said adaptive MOS transistor; and
c) an anode of said fifth diode is coupled to a voltage source, and a cathode of said fifth diode is coupled to a gate of a corresponding said adaptive MOS transistor.

### Claim 12 (depends on 1)

The adaptive cascode circuit of claim 1, wherein:
a) said adaptive MOS transistors and said main MOS transistors comprise P-type MOS transistors, said adaptive MOS transistors are coupled to at least one of a plurality of enhanced drivers, wherein each of said enhanced drivers comprises a push-pull circuit and a sixth diode;
b) an input terminal of said push-pull circuit is coupled to a corresponding said conduction clamping circuit, and an output terminal of said push-pull circuit is coupled to a gate of a corresponding said adaptive MOS transistor; and
c) a cathode of said sixth diode is coupled to a voltage source, and an anode of said sixth diode is coupled to a gate of said adaptive MOS transistor.