# US 2013/0154709 A1 · Systems and methods for output control > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0154709 A1 - Document ID: US20130154709A1 - Status: Published application - Kind: A1 - Application number: 13/683,321 - Filed: 2012-11-21 - Published: 2013-06-20 - Earliest claimed: 2011-12-15 - Assignees: Fairchild Semiconductor Corporation - Inventors: Lei Huang - Web page: https://patentgrep.com/patent/US20130154709A1 ## CPC - H03K 3/012: Modifications of generator to improve response time or to decrease power consumption - H03K 19/00315: {in field-effect transistor circuits} - H03K 3/3565: Bistables with hysteresis, e.g. Schmitt trigger - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract The present disclosure provides an output control circuit including a signal feedback circuit and an enable control circuit, wherein the signal feedback circuit is configured to compare an output voltage with a set output voltage threshold and to output a disable signal to an enable control circuit when the output voltage arrives at the set output voltage threshold, and wherein the enable control circuit is configured to stop an operation of a translation circuit, upon reception of the disable signal from the signal feedback circuit. ## Claims ### Claim 1 An output control circuit, comprising: a signal feedback circuit; and an enable control circuit, wherein the signal feedback circuit is configured to detect an output voltage, to compare the output voltage with a set output voltage threshold, and to output a disable signal to the enable control circuit when the output voltage arrives at the set output voltage threshold, and wherein the enable control circuit is configured to stop an operation of a translation circuit, upon reception of the disable signal from the signal feedback circuit. ### Claim 2 (depends on 1) The output control circuit according to claim 1, further comprising: an edge detector, configured to trigger the signal feedback circuit and the enable control circuit upon detection of an input signal. ### Claim 3 (depends on 1) The output control circuit according to claim 1, wherein the signal feedback circuit comprises a threshold detection circuit and a disable signal generation circuit, wherein the threshold detection circuit is configured to detect the output voltage, to compare the output voltage with the set output voltage threshold, and to output a trigger signal to the disable signal generation circuit when the output voltage arrives at the output voltage threshold, and wherein the disable signal generation circuit is configured to output the disable signal to the enable control circuit upon reception of the trigger signal from the threshold detection circuit. ### Claim 4 (depends on 3) The output control circuit according to claim 3, wherein the threshold detection circuit is implemented as a Schmitt input buffer. ### Claim 5 (depends on 3) The output control circuit according to claim 3, wherein the enable control circuit is specifically configured to stop outputting an enable signal to a high-drive-strength buffer based on the disable signal, in order to disable the high-drive-strength buffer. ### Claim 6 (depends on 3) The output control circuit according to claim 3, wherein the disable signal generation circuit is specifically configured to trigger an exclusive or (XOR) logic control circuit to generate the disable signal through the trigger signal. ### Claim 7 (depends on 3) The output control circuit according to claim 3, wherein the enable control circuit is specifically configured to inverse, based on the disable signal, a status of an inverter for outputting an enable signal to a high-drive-strength buffer, so as to stop outputting the enable signal to the high-drive-strength buffer. ### Claim 8 (depends on 1) The output control circuit according to claim 1, wherein the signal feedback circuit comprises a high voltage signal feedback circuit and a low voltage signal feedback circuit, wherein the high voltage signal feedback circuit is configured to detect the output voltage, to compare the output voltage with the set output voltage threshold, and to output the disable signal to the enable control circuit when the output voltage arrives at a set high voltage threshold, and wherein the low voltage signal feedback circuit is configured to detect the output voltage, to compare the output voltage with the set output voltage threshold, and to output the disable signal to the enable control circuit when the output voltage arrives at a set low voltage threshold. ### Claim 9 (depends on 8) The output control circuit according to claim 8, wherein each the high voltage signal feedback circuit and the low voltage signal feedback circuit is implemented as a comparator. ### Claim 10 (depends on 1) The output control circuit according to claim 1, wherein the enable control circuit is further configured to output an enable signal to a high-drive-strength buffer upon reception of an input enable signal. ### Claim 11 (depends on 2) The output control circuit according to claim 2, wherein the enable control circuit is further configured to output a unidirectional operation signal to the edge detector upon detecting that the translation circuit is operating unidirectionally, and wherein the edge detector triggers the signal feedback circuit and the enable control circuit based on the unidirectional operation signal. ### Claim 12 (depends on 3) The output control circuit according to claim 3, wherein the output voltage threshold contains at least one of a high voltage threshold and a low voltage threshold. ### Claim 13 An output control method, comprising: detecting an output voltage when a translation circuit is operating; comparing the output voltage with an output voltage threshold; and outputting a disable signal to stop the operation of the translation circuit when the output voltage arrives at the set output voltage threshold. ### Claim 14 (depends on 13) The output control method according to claim 13, wherein the output voltage threshold contains at least one of a high voltage threshold and a low voltage threshold. ### Claim 15 (depends on 13) The output control method according to claim 13, wherein outputting the disable signal to stop the operation of the translation circuit when the output voltage arrives at the set output voltage threshold comprises: generating a trigger signal when the output voltage arrives at the set output voltage threshold; triggering an exclusive or (XOR) logic control circuit to generate the disable signal through the trigger signal; and stopping outputting an enable signal to a high-drive-strength buffer based on the disable signal. ### Claim 16 (depends on 13) The output control method according to claim 13, wherein outputting the disable signal to stop the operation of the translation circuit when the output voltage arrives at the set output voltage threshold comprises: generating a trigger signal when the output voltage arrives at a high or low output voltage threshold; triggering an XOR logic control circuit to generate the disable signal through the trigger signal; and inversing a status of an inverter for outputting an enable signal to a high-drive-strength buffer by using the disable signal, such that the inverter stops outputting the enable signal to the high-drive-strength buffer. ### Claim 17 (depends on 13) The output control method according to claim 13, wherein outputting the disable signal to stop the operation of the translation circuit when the output voltage arrives at the set output voltage threshold comprises: detecting the output voltage and comparing the output voltage with the set output voltage threshold by using the comparator when the translation circuit is operating; generating the disable signal when the output voltage arrives at a set high or low output voltage threshold; and inversing a status of an inverter for outputting an enable signal to a high-drive-strength buffer by using the disable signal, such that the inverter stops outputting the enable signal to the high-drive-strength buffer. ### Claim 18 A translation circuit, comprising: an input buffer; a high-strength-drive buffer; and an output control circuit, wherein the input buffer provides an input signal to the output control circuit, the output control circuit controls an output signal of the high-strength-drive buffer, and wherein the output control circuit comprises a signal feedback circuit, an enable control circuit and an edge detector, the edge detector is configured to trigger the signal feedback circuit and the enable control circuit upon detection of the input signal, the signal feedback circuit is configured to detect an output voltage, to compare the output voltage with a set output voltage threshold, and to output a disable signal to the enable control circuit when the output voltage arrives at the set output voltage threshold, and the enable control circuit is configured to stop an operation of a translation circuit, upon reception of the disable signal from the signal feedback circuit. ### Claim 19 (depends on 18) The translation circuit according to claim 18, wherein the signal feedback circuit comprises a threshold detection circuit and a disable signal generation circuit, wherein the threshold detection circuit is configured to detect the output voltage, to compare the output voltage with the set output voltage threshold, and to output a trigger signal to the disable signal generation circuit when the output voltage arrives at the output voltage threshold, and wherein the disable signal generation circuit is configured to output the disable signal to the enable control circuit upon reception of the trigger signal from the threshold detection circuit. ### Claim 20 (depends on 19) The translation circuit according to claim 19, wherein the threshold detection circuit is implemented as a Schmitt input buffer. ### Claim 21 (depends on 19) The translation circuit according to claim 19, wherein the enable control circuit is specifically configured to stop outputting an enable signal to the high-drive-strength buffer based on the disable signal, in order to disable the high-drive-strength buffer. ### Claim 22 (depends on 19) The translation circuit according to claim 19, wherein the disable signal generation circuit is specifically configured to trigger an exclusive or (XOR) logic control circuit to generate the disable signal through the trigger signal. ### Claim 23 (depends on 19) The translation circuit according to claim 19, wherein the enable control circuit is specifically configured to inverse, based on the disable signal, a status of an inverter for outputting an enable signal to the high-drive-strength buffer, so as to stop outputting the enable signal to the high-drive-strength buffer. ### Claim 24 (depends on 18) The translation circuit according to claim 18, wherein the signal feedback circuit comprises a high voltage signal feedback circuit and a low voltage signal feedback circuit, wherein the high voltage signal feedback circuit is configured to detect the output voltage, to compare the output voltage with the set output voltage threshold, and to output the disable signal to the enable control circuit when the output voltage arrives at a set high voltage threshold, and wherein the low voltage signal feedback circuit is configured to detect the output voltage, to compare the output voltage with the set output voltage threshold, and to output the disable signal to the enable control circuit when the output voltage arrives at a set low voltage threshold. ### Claim 25 (depends on 24) The translation circuit according to claim 24, wherein each the high voltage signal feedback circuit and the low voltage signal feedback circuit is implemented as a comparator. ### Claim 26 (depends on 18) The translation circuit according to claim 18, wherein the enable control circuit is further configured to output an enable signal to the high-drive-strength buffer upon reception of an input enable signal. ### Claim 27 (depends on 18) The translation circuit according to claim 18, wherein the enable control circuit is further configured to output a unidirectional operation signal to the edge detector upon detecting that the translation circuit is operating unidirectionally, and wherein the edge detector triggers the signal feedback circuit and the enable control circuit based on the unidirectional operation signal. ### Claim 28 (depends on 18) The translation circuit according to claim 18, wherein the output voltage threshold contains at least one of a high voltage threshold and a low voltage threshold. ### Claim 29 A bidirectional signal interface, comprising: two or more output control circuits, wherein each of the output control circuits comprises a signal feedback circuit and an enable control circuit, wherein the signal feedback circuit is configured to detect an output voltage, to compare the output voltage with a set output voltage threshold of a bidirectional signal interface translation circuit, and to output a disable signal to the enable control circuit when the output voltage arrives at the set output voltage threshold, and wherein the enable control circuit is configured to stop an operation of the translation circuit, upon reception of the disable signal from the signal feedback circuit. ### Claim 30 (depends on 29) The bidirectional signal interface according to claim 29, wherein the output control circuit further comprises an edge detector, configured to trigger the signal feedback circuit and the enable control circuit upon detection of an input signal. ### Claim 31 (depends on 29) The bidirectional signal interface according to claim 29, wherein the signal feedback circuit comprises a threshold detection circuit and a disable signal generation circuit, wherein the threshold detection circuit is configured to detect the output voltage, to compare the output voltage with the set output voltage threshold, and to output a trigger signal to the disable signal generation circuit when the output voltage arrives at the output voltage threshold, and wherein the disable signal generation circuit is configured to output the disable signal to the enable control circuit upon reception of the trigger signal from the threshold detection circuit. ### Claim 32 (depends on 31) The bidirectional signal interface according to claim 31, wherein the threshold detection circuit is implemented as a Schmitt input buffer. ### Claim 33 (depends on 31) The bidirectional signal interface according to claim 31, wherein the enable control circuit is specifically configured to stop outputting an enable signal to a high-drive-strength buffer based on the disable signal, in order to disable the high-drive-strength buffer. ### Claim 34 (depends on 31) The bidirectional signal interface according to claim 31, wherein the disable signal generation circuit is specifically configured to trigger an exclusive or (XOR) logic control circuit to generate the disable signal through the trigger signal. ### Claim 35 (depends on 31) The bidirectional signal interface according to claim 31, wherein the enable control circuit is specifically configured to inverse, based on the disable signal, a status of an inverter for outputting an enable signal to a high-drive-strength buffer, so as to stop outputting the enable signal to the high-drive-strength buffer. ### Claim 36 (depends on 29) The bidirectional signal interface according to claim 29, wherein the signal feedback circuit comprises a high voltage signal feedback circuit and a low voltage signal feedback circuit, wherein the high voltage signal feedback circuit is configured to detect the output voltage, to compare the output voltage with the set output voltage threshold, and to output the disable signal to the enable control circuit when the output voltage arrives at a set high voltage threshold, and wherein the low voltage signal feedback circuit is configured to detect the output voltage, to compare the output voltage with the set output voltage threshold, and to output the disable signal to the enable control circuit when the output voltage arrives at a set low voltage threshold. ### Claim 37 (depends on 36) The bidirectional signal interface according to claim 36, wherein each of the high voltage signal feedback circuit and the low voltage signal feedback circuit is implemented as a comparator. ### Claim 38 (depends on 29) The bidirectional signal interface according to claim 29, wherein the enable control circuit is further configured to output an enable signal to a high-drive-strength buffer upon reception of an input enable signal. ### Claim 39 (depends on 30) The bidirectional signal interface according to claim 30, wherein the enable control circuit is further configured to output a unidirectional operation signal to the edge detector upon detecting that the translation circuit is operating unidirectionally, and wherein the edge detector triggers the signal feedback circuit and the enable control circuit based on the unidirectional operation signal. ### Claim 40 (depends on 29) The bidirectional signal interface according to claim 29, wherein the output voltage threshold contains at least one of a high voltage threshold and a low voltage threshold. ### Claim 41 An electronic apparatus, comprising: a bidirectional signal interface including two or more output control circuits, wherein each of the output control circuits comprises a signal feedback circuit and an enable control circuit, wherein the signal feedback circuit is configured to detect an output voltage, to compare the output voltage with a set output voltage threshold of a bidirectional signal interface translation circuit, and to output a disable signal to the enable control circuit when the output voltage arrives at the set output voltage threshold, and wherein the enable control circuit is configured to stop an operation of the translation circuit, upon reception of the disable signal from the signal feedback circuit.