# US 2013/0154707 A1 · Recoverable and reconfigurable pipeline structure for state-retention power gating

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- Number: US 2013/0154707 A1
- Document ID: US20130154707A1
- Status: Published application
- Kind: A1
- Application number: 13/403,597
- Filed: 2012-02-23
- Published: 2013-06-20
- Earliest claimed: 2011-12-15
- Assignees: Freescale Semiconductor, Inc.
- Inventors: Shayan Zhang; William C. Moyer; Ravindraraj Ramaraju
- Web page: https://patentgrep.com/patent/US20130154707A1

## CPC

- H03K 3/35606: {with synchronous operation}
- H03K 3/356008: {ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00)}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A system, electronic circuit, and method are disclosed. A method embodiment comprises receiving a control signal associated with a power gating operation mode of an electronic circuit, applying a reference voltage to the electronic circuit based upon the power gating operation mode, and maintaining data representing a state of a logic stage of the electronic circuit based upon the power gating operation mode. Maintaining comprises, in the described embodiment, storing data of a state of a first logic stage of the electronic circuit within a first storage element in a first power gating operation mode, and recovering data of a state of a second logic stage of the electronic circuit utilizing the data of the state of the first logic stage of the electronic circuit within the first storage element in a second power gating operation mode.

## Claims

### Claim 1

A method comprising:
receiving a control signal associated with a power gating operation mode of an electronic circuit; and
maintaining data representing a state of a logic stage of said electronic circuit based upon said power gating operation mode, wherein said maintaining comprises
storing data of a state of a first logic stage of said electronic circuit within a first storage element in a first power gating operation mode, and
recovering data of a state of a second logic stage of said electronic circuit utilizing said data of said state of said first logic stage of said electronic circuit within said first storage element in a second power gating operation mode.

### Claim 2 (depends on 1)

The method of claim 1, wherein:
said recovering data of said state of said second logic stage of said electronic circuit comprises storing said data of said state of said second logic stage within a second storage element;
said storing data of said state of said first logic stage of said electronic circuit within said first storage element comprises storing data of said state of said first logic stage of said electronic circuit within a state-retention storage element having a plurality of rail voltage inputs; and
said storing said data of said state of said second logic stage within a second storage element comprises storing said data of said state of said second logic stage within a flow-through storage element having a single rail voltage input and a flow-through control signal input, which causes said flow-through storage element to switch between level-sensitive and edge-sensitive operation.

### Claim 3 (depends on 2)

The method of claim 2, wherein:
said flow-through storage element comprises a level-sensitive scan design (LSSD) flip flop storage element;
said flow-through control signal input comprises a first clock signal input and a second clock signal input; and
said recovering data of said state of said second logic stage of said electronic circuit comprises providing a first clock signal at said first clock signal input and a second clock signal at said second clock signal input, each at a predetermined logical level associated with said second power gating operation mode.

### Claim 4 (depends on 2)

The method of claim 2, wherein:
said flow-through storage element comprises a multiplexer to select between a data input and a scan input;
said flow-through control signal input comprises a multiplexer control signal input of said multiplexer; and
said recovering data of said state of said second logic stage of said electronic circuit comprises providing a multiplexer control signal at said multiplexer control signal input at a predetermined logical level associated with said second power gating operation mode.

### Claim 5 (depends on 2)

The method of claim 2, wherein:
said maintaining data representing said state of said logic stage of said electronic circuit based upon said power gating operation mode comprises,
recovering data of a state of a third logic stage of said electronic circuit utilizing said data of said state of said second logic stage of said electronic circuit within said second storage element in said second power gating operation mode;
said recovering data of said state of said second logic stage and recovering said data of said state of said third logic stage are performed sequentially to limit an inrush current associated with said electronic circuit.

### Claim 6 (depends on 5)

The method of claim 5, wherein:
said recovering data of said state of said third logic stage of said electronic circuit comprises storing said data of said state of said third logic stage within a third storage element;
said second storage element comprises a first flow-through storage element and said third storage element comprises a second flow-through storage element;
said maintaining data representing said state of said logic stage of said electronic circuit based upon said power gating operation mode comprises
sequentially providing a first flow-through control signal at a predetermined logic level to a first flow-through control signal input of said first flow-through storage element and then a second flow-through control signal at said predetermined logic level to a second flow-through control signal input of said second flow-through storage element.

### Claim 7 (depends on 6)

The method of claim 6, wherein:
said sequentially providing comprises pulsing said first flow-through control signal and said second flow-through control signal at said predetermined logic level.

### Claim 8 (depends on 5)

The method of claim 5, further comprising:
entering a built in self test (BIST) operation mode of said electronic circuit; and
merging said second logic stage and said third logic stage into a unified logic stage in response to entry into said BIST operation mode.

### Claim 9 (depends on 8)

The method of claim 8, further comprising:
providing a clock signal to each of said second logic stage and said third logic stage, wherein
said merging said second logic stage and said third logic stage into said unified logic stage comprises varying a frequency of said clock signal.

### Claim 10 (depends on 8)

The method of claim 8, wherein:
said merging said second logic stage and said third logic stage into said unified logic stage comprises,
configuring said second storage element as a flow-through buffer in a first BIST operation mode; and
configuring said second storage element as a clocked flip-flop in a second BIST operation mode.

### Claim 11 (depends on 8)

The method of claim 8, said method further comprising:
determining a timing characteristic of said second storage element in response to said merging.

### Claim 12

An electronic circuit comprising:
a plurality of logic stages comprising a first logic stage and a second logic stage;
a first storage element coupled to said first logic stage to store data of a state of said first logic stage in a first power gating operation mode;
a second storage element coupled to said second logic stage and to said first logic stage to recover data of a state of said second logic stage utilizing data of said state of said first logic stage received via said first storage element in a second power gating operation mode; and
an input to receive a control signal specifying at least one of said first power gating operation mode and said second power gating operation mode.

### Claim 13 (depends on 12)

The electronic circuit of claim 12, wherein:
said first storage element comprises a state-retention storage element having a plurality of rail voltage inputs; and
said second storage element comprises a flow-through storage element having a single rail voltage input and a flow-through control signal input, which causes said flow-through storage element to switch between level-sensitive and edge-sensitive operation.

### Claim 14 (depends on 13)

The electronic circuit of claim 13, wherein:
said flow-through storage element comprises a level-sensitive scan design (LSSD) flip flop storage element; and
said LSSD flip flop storage element comprises a first input to receive a first clock signal and a second input to receive a second clock signal.

### Claim 15 (depends on 13)

The electronic circuit of claim 13, wherein:
said flow-through storage element comprises a multiplexer to select between a data input and a scan input.

### Claim 16 (depends on 12)

The electronic circuit of claim 12, wherein:
said electronic circuit further comprises a third storage element coupled to said second logic stage;
each of said second storage element and said third storage element comprise an input to sequentially receive a corresponding one of a plurality of flow-through control signals at a predetermined logic level; and
upon receipt of a corresponding one of said plurality of flow-through control signals at said predetermined logic level, each of said second storage element and said third storage element enters a level-sensitive mode of operation.

### Claim 17 (depends on 12)

The electronic circuit of claim 12, wherein said electronic circuit comprises a microcontroller.

### Claim 18 (depends on 12)

The electronic circuit of claim 12, wherein said electronic circuit comprises a microprocessor.

### Claim 19 (depends on 12)

The electronic circuit of claim 12, wherein:
said electronic circuit further comprises an electronic circuit reconfiguration register; and
said electronic circuit reconfiguration register comprises a plurality of bits to store data specifying at least one of said first power gating operation mode and said second power gating operation mode.

### Claim 20 (depends on 12)

A system comprising:
a sensor;
a microcontroller coupled to said sensor, said microcontroller comprising the electronic circuit of claim 12.