# US 2013/0154706 A1 · Semiconductor chip and semiconductor device

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- Number: US 2013/0154706 A1
- Document ID: US20130154706A1
- Status: Published application
- Kind: A1
- Application number: 13/735,661
- Filed: 2013-01-07
- Published: 2013-06-20
- Earliest claimed: 2005-11-21
- Assignees: Renesas Electronics Corporation
- Inventors: Tomoaki ISOZAKI
- Web page: https://patentgrep.com/patent/US20130154706A1

## CPC

- H03K 19/018592: {with a bidirectional operation}
- H03K 3/038: Multistable circuits
- H03K 19/018521: {of complementary type, e.g. CMOS}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10W 90/00: Package configurations
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a first semiconductor chip operating at a first power supply voltage and a second semiconductor chip operating at a second power supply voltage lower than the first power supply voltage to supply the second power supply voltage to the first semiconductor chip. The semiconductor chips according to the present invention are conveniently used for fabrication of the semiconductor device. The first semiconductor chip includes an output circuit including a first transistor and a second transistor, interconnected in series and turned on or off complementarily. The output circuit outputs a signal to a first external output terminal. The first semiconductor chip also includes a third transistor connected in series with the first and second transistors and having a gate electrode connected to a second output terminal. The entire chip area is reduced, as compared with the case where plural semiconductor chips, operated at different operating voltages, are interconnected and used as such in a semiconductor device provided with an input/output buffer operating at a voltage different from the respective operating voltages resulting in an increased chip area.

## Claims

### Claim 1

A semiconductor chip comprising:
an output circuit including a first transistor and a second transistor, being interconnected in series and turned on or off complementarily, said output circuit outputting a signal to a first external terminal; and
a first power supply voltage supply source, and
an internal circuit outputting a signal to said output circuit;
a third transistor connected in series with said first transistor and having a gate terminal connected to a second external terminal which is connected to a power supply of an external circuit, wherein said third transistor is connected between said first supply voltage and said first transistor;
said third transistor having one terminal connected to said first power supply voltage source;
said internal circuit comprising:
a first internal circuit unit which outputs to a gate of said first transistor and
a second internal circuit unit which outputs to a gate of said second transistor,
wherein both said first and second internal circuits operating by a voltage supplied from said first power supply voltage supply source.

### Claim 2 (depends on 1)

The semiconductor chip according to claim 1 wherein
said third transistor outputs a voltage, applied to a gate electrode thereof, at another terminal thereof.

### Claim 3 (depends on 1)

The semiconductor chip according to claim 1 wherein the threshold value of said third transistor is substantially 0V.

### Claim 4 (depends on 1)

The semiconductor chip according to claim 1 further comprising:
an input circuit having an input terminal connected to said first external terminal; said input circuit being driven by two voltages, namely a voltage supplied by said first power supply voltage supply source and a voltage entered to said second external terminal.

### Claim 5 (depends on 1)

The semiconductor chip according to claim 1 wherein said first and second transistors constitute a tristate buffer.

### Claim 6 (depends on 1)

The semiconductor chip according to claim 1 wherein the voltage applied to said second external terminal is lower than the voltage supplied from said first power supply voltage supply source.

### Claim 7 (depends on 1)

The semiconductor chip according to claim 1 wherein
the second external terminal is connected to a power supply rail of the external circuit.