# US 2013/0154702 A1 · Duty cycle correction circuit and delay locked loop circuit including the same

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- Number: US 2013/0154702 A1
- Document ID: US20130154702A1
- Status: Published application
- Kind: A1
- Application number: 13/563,863
- Filed: 2012-08-01
- Published: 2013-06-20
- Earliest claimed: 2011-12-19
- Assignees: SK hynix Inc.
- Inventors: Ki Han KIM; Ja Beom KOO
- Web page: https://patentgrep.com/patent/US20130154702A1

## CPC

- H03L 7/089: the phase or frequency detector generating up-down pulses (H03L7/087 takes precedence)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

A duty cycle correction circuit includes: a duty cycle correction unit configured to correct a duty cycle of an input clock signal according to a duty cycle correction code and generate an output clock signal; a duty cycle detection section configured to detect a duty cycle of the output clock signal and generate an up-down signal; a noise detection signal generation section configured to detect a variation of the up-down signal and generate the noise detection signal; and a duty cycle correction control unit configured to generate the duty cycle correction code in response to the noise detection signal and the up-down signal.

## Claims

### Claim 1

A duty cycle correction circuit comprising:
a duty cycle correction unit configured to correct a duty cycle of an input clock signal according to a duty cycle correction code and generate an output clock signal;
a duty cycle detection section configured to detect a duty cycle of the output clock signal and generate an up-down signal;
a noise detection signal generation section configured to detect a variation of the up-down signal and generate a noise detection signal; and
a duty cycle correction control unit configured to generate the duty cycle correction code in response to the noise detection signal and the up-down signal.

### Claim 2 (depends on 1)

The duty cycle correction circuit according to claim 1, wherein the noise detection signal generation section comprises:
a noise signal generator configured to check whether the level of the up-down signal is varying or not, at each predetermined period, and generate a plurality of noise signals; and
a noise signal variation detector configured to compare the plurality of noise signals to a plurality of set signals and generate the noise detection signal.

### Claim 3 (depends on 2)

The duty cycle correction circuit according to claim 2, wherein the noise signal generator comprises:
a delay unit configured to delay the up-down signal by a predetermined unit time and generate a plurality of delayed signals;
a divider configured to divide the cycle of the up-down signal by a predetermined multiple and output a divided signal; and
a phase comparator configured to compare a phase of the divided signal to phases of the plurality of delayed signals and generate the plurality of noise signals.

### Claim 4 (depends on 3)

The duty cycle correction circuit according to claim 3, wherein the phase comparator generates the high-level noise signal when the divided signal is at a high level, and generates the low-level noise signal when the divided signal is at a low level, at rising clocks of the plurality of delayed signals.

### Claim 5 (depends on 2)

The duty cycle correction circuit according to claim 2, wherein the noise signal variation detector generates a plurality of comparison signals by comparing the levels of the plurality of noise signals to the levels of the plurality of set signals, and outputs a comparison signal to be detected, among the plurality of comparison signals, as the noise detection signal.

### Claim 6 (depends on 5)

The duty cycle correction circuit according to claim 5, wherein the noise signal variation detector generates the activated comparison signal when the levels of the noise signal and the set signal are equal to each other, and generates the deactivated comparison signal when the levels of the noise signal and the set signal are different from each other.

### Claim 7 (depends on 1)

The duty cycle correction circuit according to claim 1, wherein the duty cycle correction control unit comprises:
a counting pulse generator configured to generate a counting pulse signal in response to the noise detection signal; and
an up-down counter configured to generate the duty cycle correction code according to the up-down signal, in synchronization with the counting pulse signal.

### Claim 8 (depends on 7)

The duty cycle correction circuit according to claim 7, wherein the counting pulse generator generates the counting pulse signal when the activated noise detection signal is inputted.

### Claim 9

A duty cycle correction circuit comprising:
a duty cycle correction unit configured to correct a duty cycle of an input clock signal according to a duty cycle correction code and generate an output clock signal;
a duty cycle detection unit configured to detect a duty cycle of the output clock and generate a detection voltage and an up-down signal;
a voltage detection unit configured to generate an input noise signal according to the level of the detection voltage;
a noise detection signal generation unit configured to detect a variation of the input noise signal and generate a noise detection signal; and
a duty cycle correction control unit configured to generate the duty cycle correction code in response to the noise detection signal and the up-down signal.

### Claim 10 (depends on 9)

The duty cycle correction circuit according to claim 9, wherein the voltage detection unit comprises:
a divided signal generation section configured to compare the level of the detection voltage based on a plurality of divided voltages, and generate a plurality of divided signals; and
an input noise signal generation section configured to generate a multi-bit combination signal by combining the divided signals, and output an upper bit of the multi-bit combination signal as the input noise signal.

### Claim 11 (depends on 9)

The duty cycle correction circuit according to claim 9, wherein the voltage detection unit comprises:
a divided signal generation section configured to compare the detection voltage level to first to third divided voltages generated by dividing an external voltage level and generate first to third divided signals; and
an input noise signal generation section configured to combine the first to third divided signals to generate a two-bit combination signal indicating the level of the detection voltage, and output an upper bit of the combination signal as the input noise signal.

### Claim 12 (depends on 9)

The duty cycle correction circuit according to claim 9, wherein the noise detection signal generation unit comprises:
a noise signal generator configured to check whether the level of the input noise signal is varying or not, at each predetermined period, and generate a plurality of noise signals; and
a noise signal variation detector configured to compare the plurality of noise signals to a plurality of set signals and generate the noise detection signal.

### Claim 13 (depends on 12)

The duty cycle correction circuit according to claim 12, wherein the noise signal generator comprises:
a delay unit configured to delay the input noise signal by a predetermined unit time and generate a plurality of delayed signals;
a divider configured to divide the cycle of the input noise signal by a predetermined multiple and output a divided signal; and
a phase comparator configured to compare a phase of the divided signal to phases of the plurality of delayed signals and generate the plurality of noise signals.

### Claim 14 (depends on 13)

The duty cycle correction circuit according to claim 13, wherein the phase comparator generates the high-level noise signal when the divided signal is at a high level, and generates the low-level noise signal when the divided signal is at a low level, at rising clocks of the plurality of delayed signals.

### Claim 15 (depends on 12)

The duty cycle correction circuit according to claim 12, wherein the noise signal variation detector generates a plurality of comparison signals by comparing the levels of the plurality of noise signals to the levels of the plurality of set signals, and outputs a comparison signal to be detected, among the plurality of comparison signals, as the noise detection signal.

### Claim 16 (depends on 15)

The duty cycle correction circuit according to claim 15, wherein the noise signal variation detector generates the activated comparison signal when the levels of the noise signal and the set signal are equal to each other, and generates the deactivated comparison signal when the levels of the noise signal and the set signal are different from each other.

### Claim 17 (depends on 9)

The duty cycle correction circuit according to claim 9, wherein the duty cycle correction control unit comprises:
a counting pulse generator configured to generate a counting pulse signal in response to the noise detection signal; and
an up-down counter configured to generate the duty cycle correction code according to the up-down signal, in synchronization with the counting pulse signal.

### Claim 18 (depends on 17)

The duty cycle correction circuit according to claim 17, wherein the counting pulse generator generates the counting pulse signal when the activated noise detection signal is inputted.

### Claim 19

A delay locked loop (DLL) circuit comprising:
a variable delay unit configured to adjust a delay amount of an external clock signal according to a phase detection signal and output a DLL clock signal;
a delay model unit configured to receive the DLL clock signal and generate a feedback clock signal by delaying the DLL clock signal by a model delay value;
a feedback phase comparison unit configured to compare phases of the feedback clock signal and the external clock signal and generate the phase detection signal according to a comparison result;
a detection unit configured to generate an up-down signal by detecting a duty cycle of the DLL clock signal, and generate a noise detection signal by detecting a variation in duty cycle of the DLL clock signal;
a duty cycle correction control unit configured to generate a duty cycle correction code in response to the noise detection signal and the up-down signal; and
a duty cycle correction unit configured to correct a duty cycle of the external clock signal according to the duty cycle correction code.

### Claim 20 (depends on 19)

The DLL circuit according to claim 19, wherein the duty cycle correction unit corrects the duty cycle of the DLL clock signal according to the duty cycle correction code.

### Claim 21 (depends on 19)

The DLL circuit according to claim 19, wherein the detection unit comprises:
a duty cycle detection section configured to detect the duty cycle of the DLL clock signal and generate the up-down signal; and
a noise detection signal generation section configured to detect a variation of the up-down signal and generate the noise detection signal.

### Claim 22 (depends on 21)

The DLL circuit according to claim according to claim 21, wherein the noise detection signal generation section comprises:
a noise signal generator configured to check whether the level of the up-down signal is varying or not, at each predetermined period, and generate a plurality of noise signals; and
a noise signal variation detector configured to compare the plurality of noise signals to a plurality of set signals and generate the noise detection signal.

### Claim 23 (depends on 22)

The DLL circuit according to claim 22, wherein the noise signal generator comprises:
a delay unit configured to delay the up-down signal by a predetermined unit time and generate a plurality of delayed signals;
a divider configured to divide the cycle of the up-down signal by a predetermined multiple and output a divided signal; and
a phase comparator configured to compare a phase of the divided signal to phases of the plurality of delayed signals and generate the plurality of noise signals.

### Claim 24 (depends on 23)

The DLL circuit according to claim 23, wherein the phase comparator generates the high-level noise signal when the divided signal is at a high level, and generates the low-level noise signal when the divided signal is at a low level, at rising clocks of the plurality of delayed signals.

### Claim 25 (depends on 22)

The DLL circuit according to claim 22, wherein the noise signal variation detector generates a plurality of comparison signals by comparing the levels of the plurality of noise signals to the levels of the plurality of set signals, and outputs a comparison signal to be detected, among the plurality of comparison signals, as the noise detection signal.

### Claim 26 (depends on 25)

The DLL circuit according to claim 25, wherein the noise signal variation detector generates the activated comparison signal when the levels of the noise signal and the set signal are equal to each other, and generates the deactivated comparison signal when the levels of the noise signal and the set signal are different from each other.

### Claim 27 (depends on 19)

The DLL circuit according to claim 19, wherein the duty cycle correction control unit comprises:
a counting pulse generator configured to generate a counting pulse signal in response to the noise detection signal; and
an up-down counter configured to generate the duty cycle correction code according to the up-down signal, in synchronization with the counting pulse signal.

### Claim 28

A DLL circuit comprising:
a variable delay unit configured to adjust a delay amount of an external clock signal according to a phase detection signal and output a DLL clock signal;
a delay model unit configured to receive the DLL clock signal and generate a feedback clock signal by delaying the DLL clock signal by a model delay value;
a feedback phase comparison unit configured to compare phases of the feedback clock signal and the external clock signal and generate the phase detection signal according to the comparison result;
a duty cycle detection unit configured to detect a duty cycle of the DLL clock and generate a detection voltage and an up-down signal;
a voltage detection unit configured to generate an input noise signal according to the level of the detection voltage;
a noise detection signal generation unit configured to detect a variation of the input noise signal and generate a noise detection signal;
a duty cycle correction control unit configured to generate a duty cycle correction code in response to the noise detection signal and the up-down signal; and
a duty cycle correction unit configured to correct a duty cycle of the external clock signal according to the duty cycle correction code.

### Claim 29 (depends on 28)

The DLL circuit according to claim 28, wherein the duty cycle correction unit corrects the duty cycle of the DLL clock signal according to the duty cycle correction code.

### Claim 30 (depends on 28)

The DLL circuit according to claim 28, wherein the voltage detection unit comprises:
a divided signal generation section configured to compare the level of the detection voltage based on a plurality of divided voltages, and generate a plurality of divided signals; and
an input noise signal generation section configured to generate a multi-bit combination signal by combining the divided signals, and output an upper bit of the multi-bit combination signal as the input noise signal.

### Claim 31 (depends on 28)

The DLL circuit according to claim 28, wherein the noise detection signal generation unit comprises:
a noise signal generator configured to check whether the level of the input noise signal is varying or not, at each predetermined period, and generate a plurality of noise signals; and
a noise signal variation detector configured to compare the plurality of noise signals to a plurality of set signals and generate the noise detection signal.

### Claim 32 (depends on 31)

The DLL circuit according to claim 31, wherein the noise signal generator comprises:
a delay unit configured to delay the input noise signal by a predetermined unit time and generate a plurality of delayed signals;
a divider configured to divide the cycle of the input noise signal by a predetermined multiple and output a divided signal; and
a phase comparator configured to compare a phase of the divided signal to phases of the plurality of delayed signals and generate the plurality of noise signals.

### Claim 33 (depends on 32)

The DLL circuit according to claim 32, wherein the phase comparator generates the high-level noise signal when the divided signal is at a high level, and generates the low-level noise signal when the divided signal is at a low level, at rising clocks of the plurality of delayed signals.

### Claim 34 (depends on 31)

The DLL circuit according to claim 31, wherein the noise signal variation detector generates a plurality of comparison signal by comparing the levels of the plurality of noise signals to the levels of the plurality of set signals, and outputs a comparison signal to be detected, among the plurality of comparison signals, as the noise detection signal.

### Claim 35 (depends on 34)

The DLL circuit according to claim 34, wherein the noise signal variation detector generates the activated comparison signal when the levels of the noise signal and the set signal are equal to each other, and generates the deactivated comparison signal when the levels of the noise signal and the set signal are different from each other.

### Claim 36 (depends on 28)

The DLL circuit according to claim 28, wherein the duty cycle correction control unit comprises:
a counting pulse generator configured to generate a counting pulse signal in response to the noise detection signal; and
an up-down counter configured to generate the duty cycle correction code according to the up-down signal, in synchronization with the counting pulse signal.