# US 2013/0154697 A1 · Pll circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0154697 A1 - Document ID: US20130154697A1 - Status: Published application - Kind: A1 - Application number: 13/711,821 - Filed: 2012-12-12 - Published: 2013-06-20 - Earliest claimed: 2011-12-15 - Assignees: Renesas Electronics Corporation - Inventors: Akio KATSUSHIMA - Web page: https://patentgrep.com/patent/US20130154697A1 ## CPC - H03L 7/097: using a comparator for comparing the voltages obtained from two frequency to voltage converters - H03L 7/06: using a reference signal applied to a frequency- or phase-locked loop - H03L 7/0893: {the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop} - H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) ## Abstract A PLL circuit includes: a phase comparator for detecting a phase difference between a reference signal and a feedback signal; a first charge pump for outputting a current Ipr according to a detection result of the phase comparator; a second charge pump for outputting a current Iint according to the detection result of the phase comparator; a filter for outputting a current Iprop from which a high frequency component of the Ipr is removed; an integrator for integrating the Iint; a voltage-current conversion circuit for outputting a current Ivi according to an integrated result of the integrator; and an oscillator that generates an oscillating signal of a frequency according to a current Iro, a sum of the Iprop and the Ivi, and feeds it back to the phase comparator. ## Claims ### Claim 1 A PLL circuit, comprising: a phase comparator to detect a phase difference between a reference signal and a feedback signal; first and second charge pumps each to output a current according to a detection result of the phase comparator; a filter to output a first current obtained by removing a high frequency component of the output current of the first charge pump; an integrator to integrate the output current of the second charge pump; a voltage-current conversion circuit to output a second current according to an integrated result of the integrator; and an oscillator to generate an oscillating signal of a frequency according to a third current generated by adding the first and the second currents, and to feed it back to the phase comparator. ### Claim 2 (depends on 1) The PLL circuit according to claim 1, further comprising: an adder to add the first and the second currents and to output the third current. ### Claim 3 (depends on 2) The PLL circuit according to claim 2, wherein the adder includes: a first transistor whose source is coupled to a first power supply, and whose drain and gate are coupled to a first node to which the first and the second currents are supplied; and a second transistor whose source is coupled to the first power supply, whose gate is coupled to the first node, and whose drain is coupled to the oscillator. ### Claim 4 (depends on 3) The PLL circuit according to claim 3, wherein the adder further includes: a third transistor that is provided between a drain of the first transistor and the first node, and whose gate is supplied with a bias voltage; and a fourth transistor that is provided between a drain of the second transistor and the oscillator, and whose gate is supplied with the bias voltage. ### Claim 5 (depends on 2) The PLL circuit according to claim 2, wherein the adder includes: a constant current source to send a fixed current; a first transistor whose source is coupled to a first power supply, whose drain is coupled to a first node to which the first and the second currents are supplied, and whose gate is coupled to the constant current source; a second transistor whose source is coupled to the first power supply, whose drain is coupled to the oscillator, and whose gate is coupled to the constant current source; a third transistor that is provided between the first node and the constant current source, and whose gate is supplied with a bias voltage; and a fourth transistor that is provided between a drain of the second transistor and the oscillator, and whose gate is supplied with the bias voltage. ### Claim 6 (depends on 2) The PLL circuit according to claim 2, wherein the adder outputs a current of a first node to which the first and the second currents are supplied, as it is, as the third current. ### Claim 7 (depends on 1) The PLL circuit according to claim 1, wherein the voltage-current conversion circuit includes a fifth transistor whose gate is supplied with an integrated result of the integrator, and that outputs a current flowing between its source and drain as the second current. ### Claim 8 (depends on 7) The PLL circuit according to claim 7, wherein the voltage-current conversion circuit includes a first resistance element that is coupled in series to the fifth transistor. ### Claim 9 (depends on 1) The PLL circuit according to claim 1, further comprising: a frequency divider to frequency-divide the oscillating signal of the oscillator and to output it as the feedback signal. ### Claim 10 (depends on 1) The PLL circuit according to claim 1, wherein the filter includes a second resistance element provided in series on a first signal line in which the output current of the first charge pump flows and a first capacitative element provided between the first signal line and the first power supply. ### Claim 11 (depends on 1) The PLL circuit according to claim 1, wherein the integrator includes a second capacitative element provided between a second signal line in which the output current of the second charge pump flows and a second power supply.