# US 2013/0154686 A1 · Method and Apparatus for Facilitating Communication Between Programmable Logic Circuit and Application Specific Integrated Circuit with Clock Adjustment

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- Number: US 2013/0154686 A1
- Document ID: US20130154686A1
- Status: Published application
- Kind: A1
- Application number: 13/689,719
- Filed: 2012-11-29
- Published: 2013-06-20
- Earliest claimed: 2011-11-30
- Assignees: Agate Logic, Inc.
- Inventors: Kai Keung Chan; David Tsang; Shian-Jiun Fu; Chao-Chiang Chen
- Web page: https://patentgrep.com/patent/US20130154686A1

## CPC

- H03K 19/017581: {programmable}
- H03K 3/02: Generators characterised by the type of circuit or by the means used for producing pulses (H03K3/64 - H03K3/84 take precedence)
- H03K 19/17736: Structural details of routing resources
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain.

## Claims

### Claim 1

A data processing device, comprising:
an application specific integrated circuit (“ASIC”) configured to perform a specific function in accordance with a first clock domain;
a configurable logic circuit (“CLC”) coupled to the ASIC and configured to perform a programmable logic function in accordance with a second clock domain; and
a phase adjustment circuit coupled with the CLC, and able to facilitate communication between the ASIC and the CLC in accordance with the first clock domain and the second clock domain.

### Claim 2 (depends on 1)

The device of claim 1, wherein the ASIC is a semiconductor based integrated circuit that is customized for a particular functionality.

### Claim 3 (depends on 1)

The device of claim 1, wherein the CLC is a semiconductor based field custom-programmable gate array (“cFPGA”) having a plurality of lookup tables (“LUTs”) and a plurality of nonvolatile programmable bits wherein the cFPGA is an integrated circuit able to be configured to one of user selected logic functions.

### Claim 4 (depends on 3)

The device of claim 3, wherein the phase adjustment circuit is fabricated together with the cFPGA.

### Claim 5 (depends on 3)

The device of claim 3, wherein the phase adjustment circuit includes a delay clock circuit configured to adjust a first clock in the first clock domain and adjust a second clock in the second clock domain so that data inputs between the ASIC and the CLC are captured reliably.

### Claim 6 (depends on 3)

The device of claim 3, wherein the phase adjustment circuit includes a delay clock circuit configured to adjust a first clock in the first clock domain so that data inputs between the ASIC and the CLC are captured reliably.

### Claim 7 (depends on 3)

The device of claim 3, wherein the phase adjustment circuit includes a delay clock circuit configured to adjust a second clock in the second clock domain so that data inputs between the ASIC and the CLC are captured reliably.

### Claim 8 (depends on 3)

The device of claim 3, wherein the phase adjustment circuit is configured to detect the first clock domain and the second clock domain and provides a calibration pattern to compensate phase difference to improve reliability of data capture travelling between the ASIC and the CLC in response to the first clock domain and the second clock domain.

### Claim 9 (depends on 1)

A system capable of processing digital information comprising the device of claim 1.

### Claim 10

A logic processing device, comprising:
an application specific integrated circuit (“ASIC”) configured to perform a specific function in accordance with a first clock domain, wherein the ASIC includes an ASIC transmitting component and an ASIC receiving component; and
a configurable logic circuit (“CLC”) coupled to the ASIC and configured to perform a programmable logic function in accordance with a second clock domain, the CLC configured to include a configuration storage and an input multiplexor, a programmable bit of the configuration storage allocated to control behavior of the input multiplexor, wherein the input multiplexor selects an input from one of the ASIC transmitting component and a CLC input component based on value of the programmable bit.

### Claim 11 (depends on 10)

The device of claim 10, wherein the CLC includes an output multiplexor and a CLC output component, the output multiplexor configured to forward an output to the ASIC receiving component or a CLC output component in response to the value of the programmable bit.

### Claim 12 (depends on 11)

The device of claim 11, wherein the configuration storage is configured to include a plurality of programmable bits and is able to receive a bit stream from the ASIC to program at least a portion of the plurality of programmable bits.

### Claim 13 (depends on 12)

The device of claim 12, wherein the ASIC is configured to provide signals that convey clock phase information to the CLC, and the CLC subsequently provides clock phase tuning information in accordance with the clock phase information and the second clock domain to the ASIC.

### Claim 14 (depends on 13)

The device of claim 13, wherein the ASIC is able to adjust the first clock domain in accordance with the clock phase tuning information from the CLC to improve reliability of information capture.

### Claim 15 (depends on 11)

The device of claim 11,
wherein the CLC receiving component includes an A flip-flop clocked by a clock A of the second clock domain;
wherein the CLC output component includes a B flip-flop clocked by a clock B of the second clock domain;
wherein the ASIC transmitting component includes a first flip-flop clocked by a first clock of the first clock domain; and
wherein the ASIC receiving component includes a second flip-flop clocked by a second clock of the first clock domain;

### Claim 16

A method of clock skew adjustment, comprising:
receiving an application specific integrated circuit (“ASIC”) clock information from an ASIC chip;
receiving a field programmable gate array (“FPGA”) clock information from an FPGA chip;
identifying an optimal clock frequency operable for both ASIC and FPGA chips in accordance with the ASIC clock information and the FPGA clock information; and
generating a clock output signal based on the optimal clock frequency and forwarding the clock output signal to the ASIC and the FGAP chips.

### Claim 17 (depends on 16)

The method of claim 16, further comprising modifying ASIC clock domain in accordance with the clock output signal to reduce data loss during communication between the ASIC chip and the FPGA chip.

### Claim 18 (depends on 17)

The method of claim 17, further comprising modifying FPGA clock domain in accordance with the clock output signal to reduce data loss during communication between the ASIC chip and the FPGA chip.

### Claim 19 (depends on 17)

The method of claim 17, further comprising activating the ASIC chip to perform a specific function in accordance with an ASIC clock domain; and activating the FPGA chip to perform a user selected function in accordance with a FPGA clock domain.

### Claim 20 (depends on 16)

The method of claim 16, wherein receiving an ASIC clock information from an ASIC chip includes capturing the ASIC clock information utilizing an ASIC clock frequency.