# US 2013/0154684 A1 · Bias compensation method and system for minimizing process, voltage and temperature corner variations > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0154684 A1 - Document ID: US20130154684A1 - Status: Published application - Kind: A1 - Application number: 13/328,322 - Filed: 2011-12-16 - Published: 2013-06-20 - Earliest claimed: 2011-12-16 - Assignees: Ati Technologies Ulc; Advanced Micro Devices, Inc. - Inventors: Junho J.H. Cho; Chihou C.L. Lee - Web page: https://patentgrep.com/patent/US20130154684A1 ## CPC - H03F 3/45183: {Long tailed pairs (H03F3/4521, H03F3/45237 take precedence)} - H04L 25/028: {Arrangements specific to the transmitter end} - H03F 2203/45048: Calibrating and standardising a dif amp - H03F: AMPLIFIERS - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract A system and method for calibrating bias in a data transmission system including a calibrated bias having impedance calibration for accommodating parameter variations in the data transmission system. A current mirror receives and balances bias currents between the calibrated bias and an output driver from the data transmission system. A digital compensation logic circuit is connected to the calibrated bias to adjust the calibrated bias for variations in parameters causing a current tail effect. A calibration logic circuit adjusts calibration due to variations in operational parameters, such that the tail current variations are minimized. ## Claims ### Claim 1 A system comprising: a stabilizing circuit connected to an output driver of a data transmission; and said stabilizing circuit including a digital compensation logic circuit to control corner variations. ### Claim 2 (depends on 1) The system of claim 1 wherein: said stabilizing circuit includes a calibration circuit having a calibration logic circuit to control a calibrated resister circuit for generating a bias current; and said digital compensation logic circuit receives a digital calibration signal to determine a corner state, and adjust said bias current based upon said corner state. ### Claim 3 (depends on 2) The system of claim 2 wherein: said corner state is within a range of faster to slower extreme corners than a selected corner state; and said digital compensation logic circuit decreases said bias current for faster corner states and increases bias current for slower corner states. ### Claim 4 (depends on 3) The system of claim 3 wherein: said corner state is determined according to a n-bit compensation table defining a range of 2̂n corner states; and said digital compensation logic circuit generates 16 variations of said bias current. ### Claim 5 (depends on 3) The system of claim 3 wherein said corner state is determined according to a compensation table defining a fast corner state, a selected corner state and a slow corner state; and said digital compensation logic circuit generating a decreased bias current adjustment, no bias current adjustment and an increased bias current adjustment. ### Claim 6 (depends on 3) The system of claim 3 wherein said digital compensation logic circuit includes a MOS array connected to said calibrated resistor circuit to adjust said calibrated resistance circuit in response to a corner state. ### Claim 7 (depends on 6) The system of claim 6 wherein: each MOS in said MOS array is activated or deactivated according to said corner state; in response to fast corner state, more MOS are activated than deactivated; and in response to a slow corner state, less MOS are activated than deactivated. ### Claim 8 A bias compensation circuit comprising: a compensation logic circuit operative to vary a bias current used in a current mirror to stabilize an output driver of a data transmission system; and said compensation logic circuit is responsive to an n-bit digital signal representative of a corner state of said output driver. ### Claim 9 (depends on 8) The bias compensation circuit of claim 8 wherein said digital signal defines a range from 0 to 2̂(n−1) bits corresponding to a range of slow to fast corner states. ### Claim 10 (depends on 9) The bias compensation circuit of claim 9 wherein a typical corner state is mid-range of said digital signal. ### Claim 11 (depends on 8) The bias compensation circuit of claim 8 wherein said digital signal is generated by a calibrated bias circuit, and said bias compensation logic circuit adjusts said calibrated bias circuit to vary said bias current. ### Claim 12 (depends on 8) The bias compensation circuit of claim 8 wherein: said bias current is generated by a calibrated bias block; and said compensation logic circuit is connected to said calibrated bias block to signal said calibrated bias block to vary said bias current relative to a corner state speed. ### Claim 13 (depends on 12) The bias compensation circuit of claim 12 wherein a corner state speed faster than a typical corner state results in a decreased bias current and a corner state speed faster than a typical corner state results in an increased bias current. ### Claim 14 A bias compensation method comprising: establishing a current mirror between a reference current from a calibrated bias circuit and an output current of an output driver from a data transmission circuit; varying said reference current by a varying impedance associated with differences parameters; and adjusting the varying of said reference current by differences between said data transmission circuit and operational parameters. ### Claim 15 (depends on 14) The method of claim 14 wherein said adjusting includes: determining variations in a corner state; adjusting the varying of said reference current to compensate for said variations in said corner state. ### Claim 16 (depends on 15) The method of claim 15 wherein: said variations in said corner state range from faster to slower than operational parameters; said adjusting step decreases said reference current relative to a faster corner state. ### Claim 17 (depends on 15) The method of claim 15 wherein: said variations in said corner state range from faster to slower than operational parameters; said adjusting step increases said reference current relative to a slower corner state. ### Claim 18 (depends on 15) The method of claim 15 wherein said determining step determines said corner state variations from a digital signal generated by said calibrated bias circuit. ### Claim 19 (depends on 15) The method of claim 15 wherein said adjusting step includes activating selected ones of a PMOS array to vary the output of the calibrated bias circuit. ### Claim 20 A computer readable non-transitory medium including instructions which when executed in a processing system cause the system to provide bias compensation in a transmission circuit comprising: varying a reference current by a varying impedance associated with differences in operational in operational parameters in a current mirror established between said reference current from a calibrated bias circuit and an output current of an output driver from said data transmission circuit; and adjusting the varying step in said reference current by differences between said data transmission circuit and operational parameters.