# US 2013/0154677 A1 · Apparatus and method for testing pad capacitance > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0154677 A1 - Document ID: US20130154677A1 - Status: Published application - Kind: A1 - Application number: 13/332,285 - Filed: 2011-12-20 - Published: 2013-06-20 - Earliest claimed: 2011-12-20 - Assignees: Intel Corporation - Inventors: Linda K. Sun; Harry Muljono - Web page: https://patentgrep.com/patent/US20130154677A1 ## CPC - G01R 31/2853: {Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections (G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66)} - G01N 27/228: {Circuits therefor (measuring capacitance per se G01R27/26)} - G01R 31/2884: {using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence)} - H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G01N: INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES (measuring or testing apparatus or processes other than immunoassay, involving enzymes or microorganisms C12M, C12Q) - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A pad capacitance test circuit may be coupled to one or more pads of an electronic circuit, such as a processor. The pad capacitance test circuit may be located on a die including the electronic circuit. The pad capacitance test circuit may reset a pad voltage of one or more of the pads to zero, and then couple the pad to a supply voltage through a pullup resistor for a time period. The final pad voltage at or near the end of the period of time may be measured. The pad capacitance may be determined from the measured value of the final pad voltage and known values of the supply voltage, the time period, and resistance of the pullup resistor. ## Claims ### Claim 1 A testing apparatus, comprising: an electronic circuit disposed on a die, the electronic circuit including one or more pads; and a test circuit disposed on the die and configured to: couple a first pad of the one or more pads to a supply voltage for a time period; and measure a first voltage of the first pad at a first time point at or near the end of the time period to enable a capacitance of the first pad to be determined. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the test circuit is configured to couple the first pad to the supply voltage through a pullup resistor. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the test circuit includes a calibration resistor having a same nominal value as a nominal value of the pullup resistor, and wherein the test circuit is further configured to measure a resistance value of the calibration resistor. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the test circuit is further configured to reset a voltage level of the first pad to approximately zero voltage prior to the first pad being coupled to the supply voltage. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein the test circuit includes a comparator and a voltage reference generator, and the test circuit is further configured to repeat the resetting and the coupling in successive iterations, wherein the voltage reference generator is configured to adjust a reference voltage in the successive iterations, and wherein the comparator is configured to compare the reference voltage to the first voltage to determine a value of the first voltage. ### Claim 6 (depends on 4) The apparatus of claim 4, further comprising a sequencer logic module disposed on the die and configured to: produce a reset signal to trigger the test circuit to reset the voltage level of the first pad; and produce a pullup signal to trigger the test circuit to couple the first pad to the supply voltage, the pullup signal being produced after an end of the reset signal. ### Claim 7 (depends on 6) The apparatus of claim 6, wherein the sequencer logic module is further configured to produce a comparator clock to trigger the test circuit to measure the first voltage, the comparator clock being produced after an end of the pullup signal. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein the sequencer logic module includes: a plurality of delay-based buffers coupled together in series and configured to receive an input clock signal; a first extraction logic coupled to a first start buffer and a first end buffer of the plurality of buffers and configured to produce the reset signal, the reset signal having the first logic state for a first time period; a second extraction logic coupled to a second start buffer and a second end buffer of the plurality of buffers and configured to produce the pullup signal, the pullup signal having the second logic state for a second time period; and a third extraction logic coupled to a third start buffer and a third end buffer of the plurality of buffers and configured to produce the comparator clock signal, the comparator clock signal having the third logic state for a third time period; wherein the second start buffer follows after the first end buffer and the third start buffer follows after the second end buffer in the series of buffers. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the test circuit is further configured to measure a voltage level of the first pad at a second time point after the first time point to determine a leakage current of the first pad. ### Claim 10 A testing method, comprising: resetting a voltage level at a pad, by a test circuit disposed on a die that includes the pad; coupling the pad to a supply voltage for a time period; and determining a first voltage of the pad at a first time point at or near the end of the time period. ### Claim 11 (depends on 10) The method of claim 10, wherein the determining the first voltage of the pad includes: repeating the resetting and the coupling in a plurality of successive iterations; comparing the voltage level of the pad to a reference voltage at or near the end of the time period in the successive iterations, wherein a value of the reference voltage changes over the successive iterations; and determining the first voltage based on the value of the reference voltage if an output of the comparing changes from a first logical state to a second logical state. ### Claim 12 (depends on 10) The method of claim 10, wherein the coupling the pad to the supply voltage includes coupling the pad to the supply voltage through a pullup resistor. ### Claim 13 (depends on 10) The method of claim 10, further comprising: receiving, by the test circuit, a reset signal to trigger the resetting; receiving, by the test circuit after receiving the reset signal, a pullup signal to trigger the coupling; and receiving, by the test circuit after receiving the pullup signal, a comparator clock signal to trigger the determining. ### Claim 14 (depends on 10) The method of claim 10, further comprising: determining a second voltage of the pad at a second time point after the first time point; and determining a leakage current of the pad by comparison of the second voltage to the first voltage. ### Claim 15 A computing apparatus, comprising: a processor disposed on a die and having one or more pads; and a test circuit disposed on the die, the test circuit including: a pulldown device coupled to a first pad of the one or more pads, the pulldown device being configured to receive a reset signal and to turn on a conductive path between the first pad and a ground terminal in response to the reset signal; a pullup resistor having a first terminal and a second terminal, the first terminal being coupled to the first pad and the second terminal being coupled to a pullup node; and a pullup device coupled between the pullup node and a supply node, the supply node being configured to receive a supply voltage, and the pullup device being configured to receive a pullup signal and to turn on a conductive path between the supply node and the pullup node for a time period in response to the pullup signal. ### Claim 16 (depends on 15) The apparatus of claim 15, further comprising a measurement module configured to measure a first voltage of the pad at or near the end of the time period. ### Claim 17 (depends on 16) The apparatus of claim 16, wherein the measurement module includes: a voltage reference generator configured to produce a reference voltage; and a comparator module configured to receive a comparator clock signal and to compare the reference voltage with the voltage level of the first pad in response to the comparator clock signal. ### Claim 18 (depends on 17) The apparatus of claim 17, further comprising a sequencer logic module, the sequencer logic module configured to produce: the reset signal at a first time point; the pullup signal at a second time point after the first time point; and the comparator clock at a third time point after the second time point. ### Claim 19 (depends on 16) The apparatus of claim 16, wherein the measurement module is further configured to measure a second voltage of the pad at a time point after the time period to determine a leakage current of the pad. ### Claim 20 (depends on 15) The apparatus of claim 15, wherein the test circuit further includes: a calibration resistor having a same nominal value as a nominal value of the pullup resistor; and a calibration device coupled to the supply node and the calibration resistor and configured to place a known voltage across the calibration resistor to enable a resistance value of the calibration resistor to be determined.