# US 2013/0154615 A1 · Rf power detection circuit with insensitivity to process, temperature and load impedance variation

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- Number: US 2013/0154615 A1
- Document ID: US20130154615A1
- Status: Published application
- Kind: A1
- Application number: 13/713,328
- Filed: 2012-12-13
- Published: 2013-06-20
- Earliest claimed: 2011-12-15
- Assignees: Marvell World Trade Ltd.
- Inventors: Renaldi Winoto; David M. Signoff
- Web page: https://patentgrep.com/patent/US20130154615A1

## CPC

- G06G 7/163: using a variable impedance controlled by one of the input signals, variable amplification or transfer function {(G06G7/161, G06G7/162 take precedence)}
- G01R 17/16: with discharge tubes or semiconductor devices in one or more arms of the bridge, e.g. voltmeter using a difference amplifier
- G01R 21/00: Arrangements for measuring electric power or power factor (G01R7/12 takes precedence)
- G06G 7/16: for multiplication or division {(G06G7/19 and G06G7/24 take precedence; measuring electric power G01R21/00)}
- H03D 7/1441: {using field-effect transistors (H03D7/145 takes precedence)}
- H03D 7/1458: {Double balanced arrangements, i.e. where both input signals are differential}
- H03D 7/1466: {Passive mixer arrangements}
- H03D 2200/0043: Bias and operating point
- G06G: ANALOGUE COMPUTERS (analogue optical computing devices G06E3/00)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H03D: DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER (masers, lasers H01S; circuits capable of acting both as modulator and demodulator H03C; details applicable to both modulators and frequency-changers H03C; demodulating pulses H03K9/00; transforming types of pulse modulation H03K11/00; coding, decoding or code conversion, in general H03M; repeater stations H04B7/14; demodulators adapted for AC systems of digital information transmission H04L27/00; synchronous demodulators adapted for colour television H04N9/66)

## Abstract

A circuit includes a multiplier circuit including a mixer configured to multiply a first differential input signal and a second differential input signal. The mixer includes a plurality of transistors including control terminals. The control terminals of the plurality of transistors receive a bias signal and the first differential input signal. A bias circuit is configured to generate the bias signal. The bias signal generated by the bias circuit is based on a voltage threshold of one of the plurality of transistors and a product of constant reference current and a bias resistance.

## Claims

### Claim 1

A circuit comprising:
a multiplier circuit including a mixer configured to multiply a first differential input signal and a second differential input signal,
wherein the mixer comprises a plurality of transistors including control terminals, and
wherein the control terminals of the plurality of transistors receive a bias signal and the first differential input signal;
a first differential amplifier configured to receive an output of the mixer;
a bias circuit configured to generate the bias signal, the bias signal generated by the bias circuit based on i) a voltage threshold of one of the plurality of transistors and ii) a product of constant reference current and a bias resistance,
wherein the bias circuit includes:
a current source configured to generate the constant reference current;
a bias resistance having the bias resistance and including one end in communication with the current source; and
a first transistor including a first terminal and a control terminal in communication with one end of the bias resistance,
wherein the bias signal is generated at a node between the bias resistance and the current source; and
a common mode feedback amplifier connected to an output of the first differential amplifier and having a common mode input connected to the bias circuit.

### Claim 2 (depends on 1)

The circuit of claim 1, wherein the mixer comprises a Gilbert cell mixer.

### Claim 3 (depends on 1)

The circuit of claim 1, wherein the bias circuit is configured to generate the bias signal such that a conversion gain of the mixer is substantially constant regardless of variations in process and temperature.

### Claim 4

(canceled)

### Claim 5 (depends on 1)

The circuit of claim 1, wherein the plurality of transistors are matched transistors and the first transistor is a scaled version of the plurality of transistors.

### Claim 6 (depends on 1)

The circuit of claim 1, wherein:
the plurality of transistors include a first transistor, a second transistor, a third transistor and a fourth transistor,
the bias signal and one polarity of the first differential input signal are input to the control terminals of the first transistor and the fourth transistor, and
the bias signal and another polarity of the first differential input signal are input to the control terminals of the second transistor and the third transistor.

### Claim 7 (depends on 6)

The circuit of claim 6, wherein:
one polarity of the second differential input signal is input to first terminals of the first transistor and the second transistor; and
another polarity of the second differential input signal is input to first terminals of the third transistor and the fourth transistor.

### Claim 8 (depends on 1)

The circuit of claim 1, further comprising:
a first resistance; and
a second resistance,
wherein:
the plurality of transistors include a first transistor, a second transistor, a third transistor and a fourth transistor,
terminals of the first transistor and the third transistor are in communication with a non-inverting input of the first differential amplifier and one end of the first resistance, and
terminals of the second transistor and the fourth transistor are in communication with an inverting input of the first differential amplifier and one end of the second resistance.

### Claim 9 (depends on 8)

The circuit of claim 8, wherein:
the common mode feedback amplifier includes a first input in communication with another end of the first resistance and an inverting output of the first differential amplifier, and a second input in communication with another end of the second resistance and a non-inverting output of the first differential amplifier.

### Claim 10 (depends on 1)

The circuit of claim 1, further comprising:
a transconductance amplifier including an input configured to receive the first differential input signal and to output the second differential input signal;
wherein:
the plurality of transistors include a first transistor, a second transistor, a third transistor and a fourth transistor,
the bias signal and one polarity of the first differential input signal are input to the control terminals of the first transistor and the fourth transistor,
the bias signal and another polarity of the first differential input signal are input to the control terminals of the second transistor and the third transistor,
one polarity of the second differential input signal are input to first terminals of the first transistor and the second transistor; and
another polarity of the second differential input signal are input to first terminals of the third transistor and the fourth transistor.

### Claim 11 (depends on 1)

A radio frequency (RF) power detection circuit, comprising:
the circuit of claim 1;
a voltage divider circuit having an input in communication with an output of a power amplifier and an output in communication with a first input of the multiplier circuit; and
a second differential amplifier having an input in communication with an input of the power amplifier and an output in communication with a second input of the multiplier circuit,
the first differential amplifier having an input in communication with an output of the multiplier circuit and an output configured to generate a power detection signal.

### Claim 12 (depends on 11)

The RF power detection circuit of claim 11, further comprising:
a first resistance in communication with one differential input of the first differential amplifier and one differential output of the first differential amplifier; and
a second resistance in communication with another differential input of the first differential amplifier and another differential output of the first differential amplifier.

### Claim 13 (depends on 11)

The RF power detection circuit of claim 11, further comprising:
a transconductance amplifier including an input configured to receive the first differential input signal and to output the second differential input signal, wherein a load impedance associated with the RF power detection circuit is based on a voltage associated with the first differential input signal.

### Claim at position 14

14-18. (canceled)