# US 2013/0154564 A1 · Semiconductor device for protecting secondary battery, battery pack, and electronic device using same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0154564 A1 - Document ID: US20130154564A1 - Status: Published application - Kind: A1 - Application number: 13/729,331 - Filed: 2012-12-28 - Published: 2013-06-20 - Earliest claimed: 2008-02-01 - Assignees: Ricoh Company, Ltd. - Inventors: Tomoyuki Goto - Web page: https://patentgrep.com/patent/US20130154564A1 ## CPC - H02J 7/65: against overtemperature - H01M 10/48: Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte (constructional details of current conducting connections for detecting conditions inside cells or batteries, e.g. details of voltage sensing terminals, H01M50/569) - H02J 7/663: {using battery or load disconnect circuits (H02J9/002 takes precedence)} - H02J 7/61: against overcharge - H02J 7/62: against overcurrent - H02J 7/63: against overdischarge - Y02E 60/10: Energy storage using batteries - H02J: ELECTRIC POWER NETWORKS; CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY - H01M: PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY - Y02E: REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION ## Abstract A battery pack includes a secondary battery, a discharge-control transistor, a charge-control transistor connected in series with the discharge-control transistor between a negative power source terminal of the secondary battery and a terminal of a load or a negative power source terminal of a charger, and a battery protection semiconductor device including a detection circuit that detects at least one of excessively charged, excessive discharging, overcurrent, short-circuit, and overheating states of the secondary battery, a control circuit that turns on and off the discharge-control transistor and the charge-control transistor, and a charge prevention circuit that prevents the secondary battery from being charged by turning off the charge-control transistor when a voltage of the secondary battery is not greater than a predetermined low-voltage criterial voltage variable by trimming a portion of the charge prevention circuit. The charge prevention circuit includes first and second inverter circuits. ## Claims ### Claim at position 1 1-3. (canceled) ### Claim 4 A battery pack comprising: a secondary battery; a discharge-control transistor; a charge-control transistor connected in series with the discharge-control transistor between a negative power source terminal of the secondary battery and either a terminal of a load or a negative power source terminal of a charger; and a battery protection semiconductor device for protecting the secondary battery, the battery protection semiconductor device comprising: a detection circuit to detect at least one of an excessively charged state, an excessive discharging state an overcurrent state, a short-circuit state and an overheating state of the secondary battery; a control circuit to turn on and off the discharge-control transistor and the charge-control transistor; and a charge prevention circuit to prevent the secondary battery from being charged by turning off the charge-control transistor when a voltage of the secondary battery is not greater than a predetermined low-voltage criterial voltage that is variable by trimming a portion of the charge prevention circuit, wherein the charge prevention circuit comprises: a first inverter circuit that receives a high-level signal during a charging mode, connected to both the negative power source terminal and a positive power source terminal of the secondary battery; and a second inverter circuit that receives an output from the first inverter circuit, connected to both the negative power source terminal and a positive power source terminal of the charger, and wherein an input threshold voltage of the second inverter circuit is variable by trimming a portion of the second inverter circuit, and the charge-control transistor is turned off according to an output from the second inverter circuit when the voltage of the secondary battery is not greater than the low-voltage criterial voltage. ### Claim 5 (depends on 4) The battery pack according to claim 4, wherein the input threshold voltage of the second inverter circuit is raised by trimming a portion thereof. ### Claim 6 (depends on 5) The battery pack according to claim 5, wherein the second inverter circuit comprises: a second PMOS transistor whose gate and source are connected to an output terminal of the first inverter circuit and the positive power source terminal of the charger, respectively; a depression-type NMOS transistor whose gate is connected to the negative power source terminal of the charger; at least one resistor connected serially between a source of the depression-type NMOS transistor and the negative power source terminal of the charger; and a trimming fuse connected in parallel to each of the at least one resistor, wherein a function node between drains of the second PMOS transistor and the depression-type NMOS transistor serves as an output terminal of the second inverter circuit. ### Claim 7 (depends on 5) The battery pack according to claim 5, wherein the second inverter circuit comprises: a second PMOS transistor whose gate and source are connected to an output terminal of the first inverter circuit and the positive power source terminal of the charger, respectively; a first depression-type NMOS transistor whose gate, source, and back gate are connected to the negative power source terminal of the charger; at least one second depression-type NMOS transistor whose gate and back gate are respectively connected to a source thereof and the negative voltage terminal of the charger, connected serially between a drain of the second PMOS transistor and a drain of the first depression-type NMOS transistor; and a trimming fuse connected between a source and a drain of each of the at least one second depression-type NMOS transistor. ### Claim 8 (depends on 5) The battery pack according to claim 5, wherein the inverter circuit comprises: a second PMOS transistor whose gate and source are connected to an output terminal of the first inverter circuit and the positive power source terminal of the charger, respectively; a first depression-type NMOS transistor whose gate, source, and back gate are connected to the negative power source terminal of the charger; at least one second depression-type NMOS transistor whose gate and back gate are respectively connected to the negative voltage terminal of the charger and a source thereof, connected serially between a drain of the second PMOS transistor and a drain of the first depression-type NMOS transistor; and a trimming fuse connected between a source and a drain of each of the at least one second depression-type NMOS transistor. ### Claim 9 (depends on 5) The battery pack according to claim 5, wherein the second inverter circuit comprises: a second PMOS transistor whose gate and source are connected to an output terminal of the first inverter circuit and the positive power source terminal of the charger, respectively; a first depression-type NMOS transistor whose gate, source, and back gate are connected to the negative power source terminal of the charger; at least one second depression-type NMOS transistor whose gate and back gate are connected to the negative voltage terminal of the charger, connected serially between a drain of the second PMOS transistor and a drain of the first depression-type NMOS transistor; and a trimming fuse connected between a source and a drain of each of the at least one second depression-type NMOS transistor. ### Claim 10 (depends on 4) The battery pack according to claim 4, wherein the input threshold voltage of the second inverter circuit is lowered by trimming. ### Claim 11 (depends on 10) The battery pack according to claim 10, wherein the second inverter circuit comprises: a second PMOS transistor whose gate is connected to an output terminal of the first inverter circuit; a depression-type NMOS transistor whose gate and source are connected to the negative power source terminal of the charger; at least one diode-connected PMOS transistor connected serially between a source of the second PMOS transistor and the positive power source terminal of the charger; and a trimming fuse connected between a source and a drain of each of the at least one diode-connected PMOS transistor, wherein a junction node between drains of the second PMOS transistor and the depression-type NMOS transistor serves as an output terminal of the second inverter circuit. ### Claim 12 (depends on 4) The battery pack according to claim 4, wherein the second inverter circuit comprises: a second PMOS transistor whose gate is connected to an output terminal of the first inverter circuit; at least one diode-connected PMOS transistor connected serially between a source of the second PMOS transistor and the positive power source terminal of the charger; a trimming fuse connected between a source and a drain of each of the at least one diode-connected PMOS transistor; a depression-type NMOS transistor whose gate is connected to the negative power source terminal of the charger; at least one resistor connected serially between a source of the depression-type NMOS transistor and the negative power source terminal of the charger; and a trimming fuse connected in parallel to each of the at least one resistor, wherein a junction node between drains of the second PMOS transistor and the depression-type NMOS transistor serves as an output terminal of the second inverter circuit. ### Claim 13 (depends on 4) The battery pack according to claim 4, wherein the second inverter circuit comprises: a second PMOS transistor whose gate is connected to an output terminal of the first inverter circuit; at least one diode-connected PMOS transistor connected serially between a source of the second PMOS transistor and the positive power source terminal of the charger; a trimming fuse connected between a source and a drain of each of the at least one diode-connected PMOS transistor; a first depression-type NMOS transistor whose gate is connected to the negative power source terminal of the charger; at least one second depression-type NMOS transistor whose gate and back gate are respectively connected to a source thereof and the negative voltage terminal of the charger, connected serially between a drain of the second PMOS transistor and a drain of the first depression-type NMOS transistor; and a trimming fuse connected between a source and a drain of each of the at least one second depression-type NMOS transistor. ### Claim 14 (depends on 4) The battery pack according to claim 4, wherein the second inverter circuit comprises: a second PMOS transistor whose gate is connected to an output terminal of the first inverter circuit; at least one diode-connected PMOS transistor connected serially between a source of the second PMOS transistor and the positive power source terminal of the charger; a trimming fuse connected between a source and a drain of each of the at least one diode-connected PMOS transistor; a first depression-type NMOS transistor whose gate, source, and back gate are connected to the negative power source terminal of the charger; at least one second depression-type NMOS transistor whose gate and back gate are respectively connected to the negative voltage terminal of the charger and a source thereof, connected serially between a drain of the second PMOS transistor and a drain of the first depression-type NMOS transistor; and a trimming fuse connected between a source and a drain of each of the at least one second depression-type NMOS transistor. ### Claim 15 (depends on 4) The battery pack according to claim 4, wherein the second inverter circuit comprises: a second PMOS transistor whose gate is connected to an output terminal of the first inverter circuit; at least one diode-connected PMOS transistor connected serially between a source of the second PMOS transistor and the positive power source terminal of the charger; a trimming fuse connected between a source and a drain of each of the at least one diode-connected PMOS transistor; a first depression-type NMOS transistor whose gate, source, and hack gate are connected to the negative power source terminal of the charger; at least one second depression-type NMOS transistor whose gate and back gate are connected to the negative voltage terminal of the charger, connected serially between a drain of the second PMOS transistor and a drain of the first depression-type NMOS transistor; and a trimming fuse connected between a source and a drain of each of the at least one second depression-type NMOS transistor. ### Claim 16 (depends on 4) The battery pack according to claim 4, wherein an input threshold voltage of the first inverter circuit is variable by trimming a portion thereof as well as that of the second inverter circuit. ### Claim 17 (depends on 16) The battery pack according to claim 16, wherein he input threshold voltage of the second, inverter circuit raised by trimming a portion thereof. ### Claim 18 (depends on 16) The battery pack according to claim 16, wherein the second inverter circuit comprises: a second PMOS transistor whose gate and source are connected to an output terminal of the first inverter circuit and the positive power source terminal of the charger, respectively: a depression-type NMOS transistor whose gate is connected to the negative power source terminal of the charger; at least one resistor connected serially between a source of the depression-type NMOS transistor and the negative power source terminal of the charger; and a trimming fuse connected in parallel to each of the at least one resistor, wherein a junction node between drains of the second PMOS transistor and the depression-type NMOS transistor serves as an output terminal of the second inverter circuit. ### Claim 19 (canceled) ### Claim 20 A battery protection semiconductor device for protecting a secondary battery, the battery protection semiconductor device comprising: a detection circuit to detect at least one of an excessively charged state, an excessive discharging state, an overcurrent state, a short-circuit state, and an overheating state of the secondary battery; a control circuit to turn on and off the discharge-control transistor and the charge-control transistor; and a charge prevention circuit to prevent the secondary battery from being charged by turning off the charge control transistor when a voltage of the secondary battery is not greater than a predetermined low-voltage criteria voltage that is variable by trimming a portion of the charge prevention circuit.