# US 2013/0154535 A1 · Lockout switching strategy for preventing high voltage transition

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- Number: US 2013/0154535 A1
- Document ID: US20130154535A1
- Status: Published application
- Kind: A1
- Application number: 13/325,907
- Filed: 2011-12-14
- Published: 2013-06-20
- Earliest claimed: 2011-12-14
- Assignees: Caterpillar Inc.
- Inventors: Jackson Wai; Mark Hartman; Thuong Le; Jesse Gerdes
- Web page: https://patentgrep.com/patent/US20130154535A1

## CPC

- H02P 29/0241: {the fault being an overvoltage}
- H02H 3/16: responsive to fault current to earth, frame or mass (with balanced or differential arrangement H02H3/26 {; monitoring earth connection H02H5/105})
- H02P: CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H)

## Abstract

A protection circuit includes a first switch, a second switch and a third switch. The first switch, the second switch and the third switch are configured to generate lock signals indicative of an electrical voltage transition on the respective phases of a multi-phase power signal. A control circuit is configured to prevent the first switch from changing state if the second switch or third switch is changing state.

## Claims

### Claim 1

A protection circuit for limiting an electrical voltage transition on at least a first phase and a second phase of a multi-phase power bus, the protection circuit comprising:
a first switch having a first upper gate configured to control a first upper gate signal and a first lower gate configured to control a first lower gate signal, the first switch configured to control the first upper gate and the first lower gate in response to a first command signal indicative of a desired state of the first switch and generate a first lock signal indicative of an electrical voltage transition on the first phase;
a second switch having a second upper gate configured to control a second upper gate signal and a second lower gate configured to control a second lower gate signal, the second switch configured to control the second upper gate and the second lower gate in response to a second command signal indicative of a desired state of the second switch and generate a second lock signal indicative of an electrical voltage transition on the second phase;
a third switch having a third upper gate configured to control a third upper gate signal and a third lower gate configured to control a third lower gate signal, the third switch configured to control the third upper gate and the third lower gate in response to a third command signal indicative of a desired state of the third switch and generate a third lock signal indicative of an electrical voltage transition on the third phase; and
a control circuit configured to control the first switch based on the first command signal and to control the second switch based on the second command signal and to control the third switch based on the third command signal, the control circuit further configured to prevent the first switch from changing state if one of the second lock signal indicates the second switch is changing state or the third lock signal indicates the third switch is changing state.

### Claim 2 (depends on 1)

The protection circuit of claim 1 wherein the first upper gate and the first lower gate are insulated-gate bipolar transistors.

### Claim 3 (depends on 2)

The protection circuit of claim 2 wherein the second upper gate and the second lower gate are insulated-gate bipolar transistors.

### Claim 4 (depends on 1)

The protection circuit of claim 1 wherein the first upper gate and the second lower gate have a dead time and a minimum on time.

### Claim 5 (depends on 4)

The protection circuit of claim 4 wherein the first lock signal is indicative of whether the first switch is changing state, in the dead time and in the minimum on time.

### Claim 6 (depends on 1)

The protection circuit of claim 1 wherein the control circuit is a computer processor.

### Claim 7 (depends on 1)

The protection circuit of claim 1 wherein the control circuit is one of a processor, a field programmable gate array and an ASIC.

### Claim 8 (depends on 7)

The protection circuit of claim 7 further comprising a memory device programmed with computer readable instructions.

### Claim 9

A controller for a multi-phase alternating current motor, the controller comprising:
a modulator for each phase of the multi-phase alternating current motor, each modulator configured to generate a pulse width modulated signal;
a switch for each phase of the multi-phase alternating current motor, each switch responsive to a command signal for its phase and configured to supply power to a phase of the multi-phase alternating current motor, each switch having a minimum on time and dead time after changing states and the controller having a latency between the command signal changing states and a output of each switch;
a lock generator for each phase of the multi-phase alternating current motor, each lock generator configured to generate a lock signal for a period during the latency between the command signal changing states and the output of the switch, the switch changing states, the minimum on time and the dead time of the switch; and
the controller coupled with each of the modulators, each of the switches and each of the lock generators configured to prevent each switch from changing states if the lock signal for one of the phases not associated with a particular switch is received.

### Claim 10 (depends on 9)

The controller of claim 9 further comprising a processor configured as the lock generator for each phase of the multi-phase alternating current motor.

### Claim 11 (depends on 9)

The controller of claim 9 wherein the modulator is one of a space vector modulator and a triangle wave modulator.

### Claim 12 (depends on 9)

The controller of claim 9 wherein the switch for each phase of the multi-phase alternating current motor further comprises an upper gate configured to control an upper gate signal and a lower gate configured to control a lower gate signal.

### Claim 13 (depends on 12)

The controller of claim 12 wherein the upper gate and the lower gate are insulated-gate bipolar transistors.

### Claim 14 (depends on 13)

The controller of claim 13 wherein the insulated-gate bipolar transistors have a dead time and a minimum on time.

### Claim 15

A method of controlling a multi-phase alternating current motor having a multi-phase power signal, the method comprising:
generating, for each phase of the multi-phase alternating current motor, a command signal indicative of whether power should be supplied to a particular phase;
supplying power to a phase associated with the multi-phase alternating current motor using a switch having a minimum on time after changing states and a latency between a command to change states and the output of the switch;
generating a lock signal for a period during the minimum on time after changing states, the latency between the command to change states and the output of the switch and a dead time; and
preventing the switch from changing states if the lock signal for another phase indicates another phase is changing states.

### Claim 16 (depends on 15)

The method of claim 15 further comprising rotating the multi-phase alternating current motor.

### Claim 17 (depends on 15)

The method of claim 15 wherein the switch comprises two insulated-gate bipolar transistors.

### Claim 18 (depends on 15)

The method of claim 15 further comprising receiving a signal indicative of whether another phase is changing states.

### Claim 19 (depends on 18)

The method of claim 18 wherein a phase is changing states during a dead time, a minimum on time and the latency between a command to change states and the output of a switch associated with the phase.

### Claim 20 (depends on 17)

The method of claim 17 wherein the insulated-gate bipolar transistors have a dead time and a minimum on time.