# US 2013/0154128 A1 · Automatic Place and Route Method for Electromigration Tolerant Power Distribution

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- Number: US 2013/0154128 A1
- Document ID: US20130154128A1
- Status: Published application
- Kind: A1
- Application number: 13/331,329
- Filed: 2011-12-20
- Published: 2013-06-20
- Earliest claimed: 2011-12-20
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chung-Hsing Wang; King-Ho Tam; Huang-Yu Chen
- Web page: https://patentgrep.com/patent/US20130154128A1

## CPC

- H10W 20/427: {Power or ground buses}
- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- G06F 30/3947: global
- G06F 30/394: Routing (G06F30/396 takes precedence)
- G06F 2119/06: Power analysis or power optimisation
- H10D 84/981: {Power supply lines}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present disclosure relates to an electromigration tolerant power distribution network generated by an automatic place and route (APR) methodology. In some embodiments, an automatic place and route tool constructs a local power network having multi-level power rails. The multi-level power rails have interleaved segments of vertically adjacent metal layers, wherein each interleaved segment is shorter than a predetermined characteristic length corresponding to a Blech length. By limiting the length of the interleaved metallization segments, electromigration within the multi-level power rails is alleviated, allowing for the maximum current density requirement (Jmax) for mean time to failures (MTTF) to be increased.

## Claims

### Claim 1

An auto place and route method, comprising:
placing a plurality of standard cells, respective standard cells comprising one or more power taps configured to provide a connection between circuit elements within the standard cells and a local power network configured to provide power to the standard cells; and
connecting the one or more power taps to one or more multi-level power rails of the local power network, wherein the one or more power rails comprise interleaved segments of vertically adjacent metal wire layers.

### Claim 2 (depends on 1)

The method of claim 1, wherein the one or more multi-level power rails extend along boundaries of the plurality of standard cells.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
removing one or more single level power rails from within the plurality of standard cells prior to connecting the one or more power taps to the one or more multi-level power rails.

### Claim 4 (depends on 1)

The method of claim 1, wherein the plurality of standard cells are designed without one or more single level power rails.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
routing signal net wires within the plurality of standard cells on a same metal level as one of the vertically adjacent metal wire layers prior to connecting the one or more power taps to the one or more multi-level power rails; and
connecting the one or more power taps to the one or more multi-level power rails in a manner that assigns positions of the vertically adjacent metal wire layers so as to avoid coloring conflicts with the signal net wires.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
routing signal net wires within the plurality of standard cells on a same metal level as one of the vertically adjacent metal wire layers after connecting the one or more power taps to the one or more multi-level power rails; and
adjusting a location of the vertically adjacent metal wire layers within the one or more multi-level power rails to avoid coloring conflicts between the signal net wires and the multi-level power rails.

### Claim 7 (depends on 1)

The method of claim 1, wherein the one or more power taps are located at a regular pitch.

### Claim 8 (depends on 1)

The method of claim 1, wherein the adjacent metal wire layers comprise:
a first metal wire layer connected to the one or more power taps; and
a second metal wire layer connected to the first metal wire layer by way of a first metal via layer.

### Claim 9 (depends on 8)

The method of claim 8, wherein the one or more power taps comprise a metal via layer vertically located between the device and the first metal wire layer.

### Claim 10 (depends on 8)

The method of claim 8, wherein the first metal wire layer and the second metal wire layer have a length corresponding to a Blech length.

### Claim 11

An integrated chip, comprising:
a plurality of standard cells, respective standard cells comprising one or more semiconductor devices;
one or more power taps comprised within each standard cell and connected to the one or more semiconductor devices; and
one or more multi-level power rails connected to the one or more power taps and comprising interleaved segments of vertically adjacent metal wire layers, wherein the one or more multi-level power rails are configured to provide power to the plurality of standard cells.

### Claim 12 (depends on 11)

The integrated chip of claim 11, wherein the one or more power taps are located at a regular pitch.

### Claim 13 (depends on 11)

The integrated chip of claim 11, wherein the vertically adjacent metal wire layers comprise:
a first metal wire layer connected to the one or more power taps; and
a second metal wire layer vertically adjacent to the first metal wire layer and connected to the first metal wire layer by way of a first metal via layer.

### Claim 14 (depends on 13)

The integrated chip of claim 13, wherein the one or more power taps are further connected to a metal wire layer in direct contact with the one or more semiconductor devices.

### Claim 15 (depends on 13)

The integrated chip of claim 13, wherein the second metal wire layer is connected to a semiconductor device by way of a vertical via chain comprising one of the one or more power taps.

### Claim 16 (depends on 13)

The integrated chip of claim 13, wherein the first and second metal wire layers have a length corresponding to a Blech length.

### Claim 17 (depends on 13)

The integrated chip of claim 13, wherein the vertically adjacent metal wire layers further comprise:
a third metal wire layer connected to the second metal wire layer by way of a second metal via layer.

### Claim 18

An auto place and route method, comprising:
placing a plurality of standard cells comprising one or more semiconductor devices within an integrated chip layout; and
forming a local power network comprising multi-level power rails having interleaved segments of vertically adjacent metal wire layers, wherein the interleaved segments have lengths that are shorter than a characteristic length corresponding to a Blech length.

### Claim 19 (depends on 18)

The method of claim 18, wherein forming a local power network comprises:
providing one or more power taps within each of the plurality of standard cells; and
connecting the one or more semiconductor devices to the multi-level power rails by way of the one or more power taps.

### Claim 20 (depends on 19)

The method of claim 19, further comprising:
routing signal net wires within the plurality of standard cells on a same metal level as one of the vertically adjacent metal wire layers; and
selecting a position of the vertically adjacent metal wire layers that avoids coloring conflicts between the one of the multiple vertically adjacent metal wire layers and the signal net wires;
wherein the signal net wires and the one of the vertically adjacent metal wire layers are fabricated using a multiple patterning lithography exposure.