# US 2013/0154119 A1 · Integrated circuit packaging system with terminals and method of manufacture thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0154119 A1 - Document ID: US20130154119A1 - Status: Published application - Kind: A1 - Application number: 13/326,806 - Filed: 2011-12-15 - Published: 2013-06-20 - Earliest claimed: 2011-12-15 - Assignees: STATS ChipPAC, Ltd. - Inventors: Byung Tai Do; Arnel Senosa Trasporto; Linda Pei Ee Chua - Web page: https://patentgrep.com/patent/US20130154119A1 ## CPC - H10W 70/457: {of metallic layers on leadframes} - H10W 70/04: of leadframes - H10W 70/479: {on or in insulating or insulated package substrates, interposers, or redistribution layers} - H10W 74/111: {the semiconductor body being completely enclosed} - H10W 70/042: {Etching} - H10W 70/682: {comprising holes having chips therein} - H10W 72/0198: {batch processes} - H10W 72/07254: {changes in dispositions} - H10W 72/073: {of die-attach connectors} - H10W 72/075: {of bond wires} - H10W 72/07552: {changes in structures or sizes} - H10W 72/07554: {changes in dispositions} - H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/247: {Dispositions of multiple bumps} - H10W 72/354: {comprising polymers} - H10W 72/521: {Structures or relative sizes of bond wires} - H10W 72/547: {Dispositions of multiple bond wires} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method of manufacture of an integrated circuit packaging system includes: forming a lead having a lead top side; forming a lower interior conductive layer directly on the lead top side; forming an interior insulation layer directly on the lower interior conductive layer; forming an upper interior conductive layer directly on the interior insulation layer; and mounting an integrated circuit over the upper interior conductive layer. ## Claims ### Claim 1 A method of manufacture of an integrated circuit packaging system comprising: forming a lead having a lead top side; forming a lower interior conductive layer directly on the lead top side; forming an interior insulation layer directly on the lower interior conductive layer; forming an upper interior conductive layer directly on the interior insulation layer; and mounting an integrated circuit over the upper interior conductive layer. ### Claim 2 (depends on 1) The method as claimed in claim 1 wherein mounting the integrated circuit includes mounting the integrated circuit directly over the lead. ### Claim 3 (depends on 1) The method as claimed in claim 1 further comprising: forming a package paddle adjacent the lead; and wherein: forming the lower interior conductive layer includes forming the lower interior conductive layer directly on the package paddle. ### Claim 4 (depends on 1) The method as claimed in claim 1 wherein: forming the lead includes forming the lead having a lead step portion; and forming the lower interior conductive layer includes forming the lower interior conductive layer directly on the lead step portion. ### Claim 5 (depends on 1) The method as claimed in claim 1 further comprising forming a conductive cap directly on the lead top side. ### Claim 6 A method of manufacture of an integrated circuit packaging system comprising: forming a lead having a lead top side; forming a lower interior conductive layer directly on the lead top side; forming an interior insulation layer directly on the lower interior conductive layer; forming an upper interior conductive layer directly on the interior insulation layer; mounting an integrated circuit over the upper interior conductive layer; and forming a protection layer directly on a lower layer bottom side of the lower interior conductive layer. ### Claim 7 (depends on 6) The method as claimed in claim 6 further comprising: forming a package paddle adjacent the lead; and attaching an attach layer to the package paddle and the integrated circuit. ### Claim 8 (depends on 6) The method as claimed in claim 6 further comprising attaching an internal connector to the integrated circuit and the lower interior conductive layer. ### Claim 9 (depends on 6) The method as claimed in claim 6 further comprising attaching an attach layer to the integrated circuit and the lower interior conductive layer. ### Claim 10 (depends on 6) The method as claimed in claim 6 wherein mounting the integrated circuit includes mounting a flip chip over the upper interior conductive layer. ### Claim 11 An integrated circuit packaging system comprising: a lead having a lead top side; a lower interior conductive layer directly on the lead top side; an interior insulation layer directly on the lower interior conductive layer; an upper interior conductive layer directly on the interior insulation layer; and an integrated circuit over the upper interior conductive layer. ### Claim 12 (depends on 11) The system as claimed in claim 11 wherein the integrated circuit is directly over the lead. ### Claim 13 (depends on 11) The system as claimed in claim 11 further comprising: a package paddle adjacent the lead; and wherein: the lower interior conductive layer is directly on the package paddle. ### Claim 14 (depends on 11) The system as claimed in claim 11 wherein: the lead includes a lead step portion; and the lower interior conductive layer is directly on the lead step portion. ### Claim 15 (depends on 11) The system as claimed in claim 11 further comprising a conductive cap directly on the lead top side. ### Claim 16 (depends on 11) The system as claimed in claim 11 further comprising a protection layer directly on a lower layer bottom side of the lower interior conductive layer. ### Claim 17 (depends on 16) The system as claimed in claim 16 further comprising: a package paddle adjacent the lead; and an attach layer attached to the package paddle and the integrated circuit. ### Claim 18 (depends on 16) The system as claimed in claim 16 further comprising an internal connector attached to the integrated circuit and the lower interior conductive layer. ### Claim 19 (depends on 16) The system as claimed in claim 16 further comprising an attach layer attached to the integrated circuit and the lower interior conductive layer. ### Claim 20 (depends on 16) The system as claimed in claim 16 wherein the integrated circuit is a flip chip over the upper interior conductive layer.