# US 2013/0154112 A1 · Method for Forming Isolation Trenches in Micro-Bump Interconnect Structures and Devices Obtained Thereof

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- Number: US 2013/0154112 A1
- Document ID: US20130154112A1
- Status: Published application
- Kind: A1
- Application number: 13/713,932
- Filed: 2012-12-13
- Published: 2013-06-20
- Earliest claimed: 2011-12-16
- Assignees: Katholieke Universiteit Leuven, KU LEUVEN R&D; Imec
- Inventors: Wenqi Zhang; Wei-E Wang; Geert Eneman; Eric Beyne; Andrej Ivankovic
- Web page: https://patentgrep.com/patent/US20130154112A1

## CPC

- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10P 10/12: {Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates (preparing SOI wafers using bonding H10P90/1914)}
- H10W 20/0249: {wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/217: {comprising ring-shaped isolation structures outside of the via holes}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 74/134: {the encapsulations being in grooves in the semiconductor body}
- H10W 90/00: Package configurations
- H10W 72/019: {of bond pads}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/90: Bond pads, in general
- H10W 72/921: {Structures or relative sizes of bond pads}
- H10W 72/9226: {with via interconnections}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/983: {Reinforcing structures, e.g. collars}
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The disclosure is related to a substrate suitable for use in a stack of interconnected substrates, comprising: a base layer having a front side and a back side surface parallel to the plane of the base layer; one or more interconnect structures, each of said structures comprising: a via filled with an electrically conductive material, said via running through the complete thickness of the base layer, thereby forming an electrical connection between said front side and back side surfaces of the base layer, and on the back side surface of the base layer: a landing pad and a micro-bump in electrical connection with said filled via; characterized in that the backside surface of said base layer comprises one or more isolation ring trenches each of said trenches surrounding one or more of said interconnect structures. The disclosure is equally related to methods for producing said substrates and stacks of substrates.

## Claims

### Claim 1

A substrate suitable for use in a stack of interconnected substrates, comprising:
a base layer, having a front side surface and a back side surface parallel to a plane of the base layer; and
one or more interconnect structures, each of said interconnect structures comprising:
a via filled with an electrically conductive material, said via running through a complete thickness of the base layer, thereby forming an electrical connection between said front side surface and said back side surface of the base layer, and
on the back side surface of the base layer: a landing pad and a micro-bump in electrical connection with said filled via;
characterized in that the back side surface of said base layer comprises one or more isolation ring trenches, each of said isolation ring trenches surrounding one or more of said interconnect structures.

### Claim 2 (depends on 1)

The substrate according to claim 1, wherein said isolation ring trenches are filled with a material that has a suitably low Young's modulus and a suitably low Coefficient of Thermal expansion, so as to be able to absorb a localized stress created during bonding of the substrate to another substrate in a process for forming a stack of interconnected substrates.

### Claim 3 (depends on 2)

The substrate according to claim 2, wherein said material is present in said isolation ring trenches and on the back side surface of said base layer.

### Claim 4 (depends on 1)

The substrate according to claim 1, wherein:
a first layer is present on and in contact with said back side surface of the base layer; and
said isolation ring trenches are formed through said first layer, extending into the underlying base layer.

### Claim 5 (depends on 4)

The substrate according to claim 4, wherein said isolation ring trenches and the surface of said first layer are filled with a second layer formed of a material that has a suitably low Young's modulus and a suitably low Coefficient of Thermal expansion, so as to be able to absorb a localized stress created during bonding the substrate to another substrate by forming a stack of interconnected substrates.

### Claim 6 (depends on 4)

The substrate according to claim 4, wherein said first layer is formed of a material that has a similar Young's modulus value and CTE compared to the material of the base layer into which the one or more isolation ring trenches are etched.

### Claim 7 (depends on 2)

The substrate according to claim 2, wherein said material filling said isolation ring trenches is a polyamide or BCB.

### Claim 8 (depends on 1)

The substrate according to claim 1, wherein at least one of said isolation ring trenches surrounds more than one interconnect structure.

### Claim 9 (depends on 1)

The substrate according to claim 1, wherein said substrate further comprises:
one or more integrated circuits on the front side surface of said base layer; and
on top of said one or more integrated circuits, a metallization stack of Back-end-of-line interconnect layers, wherein said filled vias establish an electrical connection between said metallization stack and the micro-bumps on the back side surface of the base layer.

### Claim 10 (depends on 9)

The substrate according to claim 9, further comprising additional landing pads on the front side surface of said base layer, each of said additional landing pads being in electrical connection with one of said filled vias, said additional landing pads being suitable for connecting the substrate to another substrate in a stacking process.

### Claim 11 (depends on 1)

The substrate of claim 1, wherein the substrate is interconnected to a second substrate through one or more through-silicon-via connections, and wherein an underfill material is present between the substrate and the second substrate.

### Claim 12 (depends on 11)

The substrate according to claim 11, wherein said isolation ring trenches are filled with a material having a lower Young's modulus value than the material into which said trenches are formed, and a lower Coefficient of Thermal expansion value than said underfill material.

### Claim 13

A method for producing a substrate suitable for use in a stack of interconnected substrates, comprising the steps of:
providing a substrate, the substrate comprising:
a base layer, having a front side and a back side parallel to a plane of the base layer,
one or more vias filled with an electrically conductive material, said vias running through a complete thickness of the base layer, said filled vias forming an electrical connection from the back side to the front side of the base layer,
etching one or more ring-shaped trenches in the back side of said base layer, each of said ring-shaped trenches surrounding one or more of said filled vias, and
on the back side of the base layer: producing a landing pad and a micro-bump in electrical connection with said filled via, wherein each of said ring-shape trenches surrounds one or more of said micro-bumps.

### Claim 14 (depends on 13)

The method according to claim 13, further comprising the step of filling said ring-shaped trenches with a material that has a suitably low Young's modulus and a suitably low Coefficient of Thermal expansion, so as to be able to absorb a localized stress created during bonding of the substrate to another substrate in a process for forming a stack of interconnected substrates.

### Claim 15

A method for producing a stack of interconnected substrates, the method comprising the steps of:
stacking two or more substrates, wherein one or more of said substrates comprises:
a base layer, having a front side surface and a back side surface parallel to a plane of the base layer;
one or more interconnect structures; and
one or more isolation ring trenches, each of said isolation ring trenches surrounding one or more of said interconnect structures;
placing an underfill material between neighbouring substrates of said substrates; and
curing said underfill material so as to form a bond between said neighbouring substrates.

### Claim 16 (depends on 15)

The method of claim 15, wherein the one or more of said substrates further comprise:
a via filled with an electrically conductive material, said via running through a complete thickness of the base layer, thereby forming an electrical connection between said front side surface and said back side surface of the base layer, and
on the back side surface of the base layer: a landing pad and a micro-bump in electrical connection with said filled via.