# US 2013/0154102 A1 · Semiconductor device and its manufacture method

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2013/0154102 A1
- Document ID: US20130154102A1
- Status: Published application
- Kind: A1
- Application number: 13/764,532
- Filed: 2013-02-11
- Published: 2013-06-20
- Earliest claimed: 2010-02-04
- Assignees: Shinko Electric Industries Co., Ltd.; Fujitsu Limited
- Inventors: Sadahiro KISHII; Tsuyoshi KANKI; Yoshihiro NAKATA; Yasushi KOBAYASHI; Masato TANAKA; Akio ROKUGAWA
- Web page: https://patentgrep.com/patent/US20130154102A1

## CPC

- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/682: {comprising holes having chips therein}
- H10W 72/0198: {batch processes}
- H10W 72/073: {of die-attach connectors}
- H10W 72/874: {On different surfaces}
- H10W 72/9413: {on encapsulations}
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A support substrate includes a first surface and a second surface located above the level of the first surface. Chips are mounted on the first surface. A first insulating film is disposed over each chip. First conductive plugs are connected to the chip extending through each first insulating film. Filler material made of resin filling a space between chips. Wirings are disposed over the first insulating film and the filler material for interconnecting different chips. The second surface, an upper surface of the first insulating film and an upper surface of the filler material are located at the same level.

## Claims

### Claim 1

A semiconductor device comprising:
a support substrate comprising a first surface and a second surface that is located on a same side of the first surface and above a level of the first surface;
chips mounted over the first surface;
first insulating films, each of which is disposed over each of the chips;
first conductive plugs formed through each of the first insulating films and connected to each of the chips; filler material made of resin and filling a space between the chips; and
wirings disposed over the first insulating films and the filler material, wherein the second surface, upper surfaces of the first insulating films, and an upper surface of the filler material are located at a same level.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein upper surfaces of the first conductive plugs and upper surfaces of the first insulating films are located at a same level.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2, further comprising:
a second insulating film disposed over the first insulating films, the filler material, and the second surface; and
second conductive plugs extending through the second insulating film, connected to the first conductive plugs, and being smaller in horizontal cross-sectional area than the first conductive plugs,
wherein the wirings are disposed over the second insulating film and connected to the first conductive plugs via the second conductive plugs.

### Claim at position 4

4-9. (canceled)

### Claim 10

A semiconductor device comprising:
a support substrate;
chips mounted on the support substrate and having pads formed over an upper surface thereof;
first insulating films, each of which is formed over each of the chips;
first conductive plugs connected to the pads and disposed in the first insulating films;
filler material made of resin filling a space between the chips and defining a flat surface together with an upper surface of the first insulating film;
a second insulating film disposed over the first insulating film and the filler material;
second conductive plugs disposed in the second insulating film and connected to the first conductive plugs, the second conductive plugs being smaller in horizontal cross-sectional area than the first conductive plugs; and
wirings formed over the second insulating film and interconnecting pads of different chips via the second conductive plug and the first conductive plug.