# US 2013/0154101 A1 · Semiconductor device and method for manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0154101 A1 - Document ID: US20130154101A1 - Status: Published application - Kind: A1 - Application number: 13/488,246 - Filed: 2012-06-04 - Published: 2013-06-20 - Earliest claimed: 2011-12-16 - Assignees: SK hynix Inc. - Inventors: Dae Sik PARK - Web page: https://patentgrep.com/patent/US20130154101A1 ## CPC - H10W 20/43: Layouts of interconnections - H10B 12/0335: {Making a connection between the transistor and the capacitor, e.g. plug} - H10B 12/31: {having a storage electrode stacked over the transistor} - H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs} - H10W 20/42: Vias, e.g. via plugs - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A semiconductor device and a method for manufacturing the same are disclosed. In the semiconductor device, an upper part of a storage node contact plug is increased in size, and an area of overlap between a storage node formed in a subsequent process and a storage node contact plug is increased, such that resistance of the storage node contact plug is increased and device characteristics are improved. The semiconductor device includes at least one bit line formed over a semiconductor substrate, a first storage node contact plug formed between the bit lines and coupled to an upper part of the semiconductor substrate, and a second storage node contact plug formed over the first storage node contact plug, wherein a width of a lower part of the second storage node contact plug is larger than a width of an upper part thereof. ## Claims ### Claim 1 A semiconductor device comprising: first and second bit lines; first and second insulating patterns provided over the first and the second bit lines, respectively; a first storage node contact plug provided between the first and the second bit lines; and a second storage node contact plug coupled to the first storage node contact plug and provided between the first and the second insulating patterns, wherein a size of the second storage node contact plug at a top surface level of the second storage node contact plug is larger than a size of the second storage node contact plug at a bottom surface level of the second storage node contact plug. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the second storage node contact plug includes a first tapered configuration, and wherein any of the first and the second insulating patterns includes a second tapered configuration that is complementary to the second storage node contact plug. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein a top surface of the first storage node contact plug extends to a higher level than top surfaces of the first and the second bit lines so that the second storage node contact plug is not coupled to any of the first and the second bit lines. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein top surfaces of first and second insulating patterns are formed at substantially the same level as a top surface of the second storage node contact plug. ### Claim 5 A semiconductor device comprising: first and second bit lines; a first storage node contact plug formed between the first and the second bit lines; and a second storage node contact plug formed at a lateral surface of and upper part of the first storage node contact plug and disposed over any of the first and the second bit lines, wherein the second storage node contact plug is formed as a spacer over the bit line hard mask. ### Claim 6 (depends on 5) The semiconductor device according to claim 5, wherein each of the first and the second bit line include a bit line conductive pattern and a bit line hard mask. ### Claim 7 (depends on 5) The semiconductor device according to claim 5, wherein each of the first storage node contact plug and the second storage node contact plug includes polysilicon or metal. ### Claim 8 (depends on 5) The semiconductor device according to claim 5, wherein an insulation material is formed over an upper part of each of the first and the second bit lines and are located between neighboring second storage node contact plugs. ### Claim 9 (depends on 5) The semiconductor device according to claim 5, wherein the first storage node contact plug extends from a first level up to a second level, wherein the second storage node contact plug extends from a third level up to a fourth level, wherein the third level is between the first and the second levels, wherein the first storage node contact plug has a first size at the third level and has a second size at the second level, wherein the second storage node contact plug has a third size at the second level, and wherein a sum of the second size and twice the third size is larger than the first size. ### Claim at position 10 10-20. (canceled) ### Claim 21 A method for manufacturing a semiconductor device comprising: providing first and second bit lines; providing first and second insulating patterns over the first and the second bit lines, respectively; providing a first storage node contact plug between the first and the second bit lines; providing a first contact hole over the first storage node contact plug and between the first and the second insulating patterns; enlarging a size of the first contact hole to form a second contact hole so that a size of a top opening of the second contact hole is larger than a size of a bottom opening of the second contact hole; and providing a second storage node contact plug in the second contact hole so that the second storage node contact plug is coupled to the first storage node contact plug.