# US 2013/0154089 A1 · Bump including diffusion barrier bi-layer and manufacturing method thereof

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- Number: US 2013/0154089 A1
- Document ID: US20130154089A1
- Status: Published application
- Kind: A1
- Application number: 13/715,124
- Filed: 2012-12-14
- Published: 2013-06-20
- Earliest claimed: 2011-12-16
- Assignees: Research & Business Foundation Sungkyunkwan University
- Inventors: Hoojeong Lee; Byunghoon Lee
- Web page: https://patentgrep.com/patent/US20130154089A1

## CPC

- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 90/00: Package configurations
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/07255: {changes in materials}
- H10W 72/221: {Structures or relative sizes}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/2528: {Intermetallic compounds}
- H10W 90/722: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Provided herein is a bump including a diffusion barrier bi-layer, the bump having: a conductive layer; a first diffusion barrier layer formed on or above the conductive layer, and comprising an alloy of nickel and phosphorus; a second diffusion barrier formed on or above the first diffusion barrier layer, and comprising copper; and a solder layer formed on or above the second diffusion barrier layer. A manufacturing method for producing a bump is also provided.

## Claims

### Claim 1

A bump including a diffusion bather bi-layer, the bump comprising:
a conductive layer;
a first diffusion barrier layer formed on or above the conductive layer, and comprising an alloy of nickel and phosphorus;
a second diffusion barrier formed on or above the first diffusion barrier layer, and comprising copper; and
a solder layer formed on or above the second diffusion barrier layer.

### Claim 2 (depends on 1)

The bump according to claim 1, wherein the bump is formed in a semiconductor 3D stacking process.

### Claim 3 (depends on 1)

The bump according to claim 1, wherein a thickness ratio of the first diffusion barrier layer and the second diffusion barrier layer ranges from 1.2:1 to 2.5:1.

### Claim 4 (depends on 1)

The bump according to claim 1, wherein a thickness of the first diffusion barrier layer ranges from 0.8 μm to 1.6 μm, and a thickness of the second diffusion barrier layer ranges from 0.4 μm to 0.8 μm.

### Claim 5 (depends on 3)

The bump according to claim 3, wherein a thickness of the first diffusion barrier layer ranges from 0.8 μm to 1.6 μm, and a thickness of the second diffusion barrier layer ranges from 0.4 μm to 0.8 μm.

### Claim 6 (depends on 1)

The bump according to claim 1, wherein the conductive layer comprises copper (Cu), and the solder layer comprises tin (Sn).

### Claim 7 (depends on 3)

The bump according to claim 3, wherein the conductive layer comprises copper (Cu), and the solder layer comprises tin (Sn).

### Claim 8 (depends on 1)

The bump according to claim 1, wherein a thickness of the conductive layer ranges from 20 μm to 60 μm, and a thickness of the solder layer ranges from 3 μm to 10 μm.

### Claim 9 (depends on 3)

The bump according to claim 3, wherein a thickness of the conductive layer ranges from 20 μm to 60 μm, and a thickness of the solder layer ranges from 3 μm to 10 μm.

### Claim 10

A manufacturing method of a bump including a diffusion barrier bi-layer, the method comprising:
forming a conductive layer by depositing copper on or above an object in an electroplating method;
forming a first diffusion barrier layer by depositing an alloy of nickel and phosphorus on or above the conductive layer in an electroless-plating method;
forming a second bather layer by depositing copper on or above the first diffusion barrier layer in an electroplating method; and
forming a solder layer by depositing tin (Sn) on or above the second diffusion barrier layer.

### Claim 11 (depends on 10)

The manufacturing method according to claim 10, wherein a semiconductor 3D stacking process is applied to form the bump.

### Claim 12 (depends on 10)

The manufacturing method according to claim 10, wherein the first diffusion barrier layer is deposited to have a thickness of 0.8 μm to 1.6 μm.

### Claim 13 (depends on 10)

The manufacturing method according to claim 10, wherein the second diffusion barrier layer is deposited to have a thickness of 0.4 μm to 0.8 μm.

### Claim 14 (depends on 10)

The manufacturing method according to claim 10, wherein the second diffusion barrier layer is deposited to have a thickness of 0.4 μm to 0.8 μm.