# US 2013/0154086 A1 · Exposing Connectors in Packages Through Selective Treatment > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2013/0154086 A1 - Document ID: US20130154086A1 - Status: Published application - Kind: A1 - Application number: 13/331,061 - Filed: 2011-12-20 - Published: 2013-06-20 - Earliest claimed: 2011-12-20 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Chen-Hua Yu; Chung-Shi Liu; Chun-Cheng Lin; Meng-Tse Chen; Ming-Da Cheng - Web page: https://patentgrep.com/patent/US20130154086A1 ## CPC - H10W 74/10: characterised by their shape or disposition - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills} - H10W 74/016: {using moulds} - H10W 74/114: {by a substrate and the encapsulations} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 70/63: Vias, e.g. via plugs - H10W 70/635: {Through-vias} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method includes performing an etching step on a package. The package includes a package component, a connector on a top surface of the package component, a die bonded to the top surface of the package component, and a molding material molded over the top surface of the package component. The molding material covers the connector, wherein a portion of the molding material covering the connector is removed by the etching step, and the connector is exposed. ## Claims ### Claim 1 A method comprising: performing an etching step on a package, wherein the package comprises: a package component; a connector on a top surface of the package component; a die bonded to the top surface of the package component; and a molding material molded over the top surface of the package component, wherein the molding material covers the connector, wherein a portion of the molding material covering the connector is removed by the etching step, and wherein the connector is exposed after the etching step. ### Claim 2 (depends on 1) The method of claim 1, wherein in the etching step, no etching mask is formed over the top surface of the package component. ### Claim 3 (depends on 1) The method of claim 1 further comprising, before the etching step, forming an etching mask over the package, wherein a first portion of the molding material over and aligned to the connector is exposed through an opening in the etching mask, and wherein a second portion of the molding material over and misaligned with the connector is covered by the etching mask. ### Claim 4 (depends on 1) The method of claim 1, wherein the etching step comprises an anisotropic etching. ### Claim 5 (depends on 1) The method of claim 1, wherein the etching step comprises an isotropic etching. ### Claim 6 (depends on 1) The method of claim 1, wherein during the etching step, a top surface of the die is used as an etching stop layer. ### Claim 7 (depends on 1) The method of claim 1, wherein the molding material comprises a polymer, a filler, and an hardener. ### Claim 8 A method comprising: bonding a die to a top surface of a package substrate, wherein the package substrate comprises a plurality of solder regions on the top surface; molding a molding material over the top surface of the package substrate, wherein the molding material covers the plurality of solder regions, and wherein the molding material comprises a polymer; and performing a treatment to remove a portion of the molding material covering the solder region, wherein after the treatment, a top portion of each of the plurality of solder regions is exposed, wherein an entirety of a top surface of a portion of the molding material is lower than top ends of the plurality of solder regions, and wherein the portion of the molding material is between two neighboring ones of the plurality of solder regions. ### Claim 9 (depends on 8) The method of claim 8, wherein after the treatment, substantially an entirety of the molding material is located below the top ends of the plurality of solder regions. ### Claim 10 (depends on 8) The method of claim 8, wherein the treatment comprises etching the molding material, and the treatment is performed without any etching mask formed over the molding material. ### Claim 11 (depends on 10) The method of claim 10, wherein the step of etching comprises a dry etching. ### Claim 12 (depends on 10) The method of claim 10, wherein the step of etching comprises a plasma etching. ### Claim 13 (depends on 10) The method of claim 10, wherein the step of etching comprises a wet etching. ### Claim 14 (depends on 10) The method of claim 10, wherein the molding material further comprises a filler and an hardener, and wherein during the step of treatment, the filler and the hardener are etched. ### Claim 15 A device comprising: a package component; a die bond to a top surface of the package component; a plurality of solder regions disposed on the top surface of the package component; and a molding material disposed over the top surface of the package component, wherein lower portions of the plurality of solder regions are disposed in the molding material, and wherein an entirety of a top surface of the molding material between two neighboring ones of the plurality of solder regions is lower than top ends of the plurality of solder regions. ### Claim 16 (depends on 15) The device of claim 15, wherein substantially an entirety of the molding material is lower than the top ends of the plurality of solder regions. ### Claim 17 (depends on 16) The device of claim 16, wherein an entirety of the surface of an entire of molding material is substantially planar, and wherein the plurality of solder regions comprises round top surfaces. ### Claim 18 (depends on 15) The device of claim 15, wherein a top surface of the die is exposed. ### Claim 19 (depends on 18) The device of claim 18, wherein the top surface of the die is higher than the entirety of the top surface of the molding material. ### Claim 20 (depends on 15) The device of claim 15, wherein the molding material comprises a polymer, a filler, and an hardener.